Speeding-up exact and fast FIFO-based cache configuration simulation

Masashi Tawada*, Masao Yanagisawa, Nozomu Togawa

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)


The number of sets, block size, and associativity determine processor's cache configurations. Particularly in embedded systems, their cache configuration can be optimized since their target applications are much limited. Recently, the CRCB method has been proposed for LRU-based (Least Recently Used-based) cache configuration simulation, which can calculate cache hit/miss counts accurately and very fast changing the three parameters. However many recent processors use FIFO-based (First-In-First-Out-based) caches instead of LRU-based caches due to the viewpoints of their hardware costs. In this paper, we propose a speeding-up cache configuration simulation method for embedded applications that uses FIFO as a cache replacement policy. We first prove several properties for FIFO-based caches and then propose a simulation method that can process two or more FIFO-based cache configurations with different cache associativities simultaneously. Experimental results show that our proposed method can obtain accurate cache hits/misses and runs up to 32% faster than the conventional simulators.

Original languageEnglish
Pages (from-to)1161-1167
Number of pages7
Journalieice electronics express
Issue number14
Publication statusPublished - 2011


  • Cache configuration optimization
  • Cache memory
  • Cache simulation
  • Embedded systems
  • FIFO

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering


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