Sub-quarter-micron dual gate CMOSFETs with ultra-thin gate oxide of 2nm

T. Kuroi*, S. Shimizu, S. Ogino, A. Teramoto, M. Shirahata, Y. Okumura, M. Inuishi, H. Miyoshi

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

11 Citations (Scopus)


The high performance 0.25 μm dual gate CMOS with ultrathin gate oxide of 2 nm is demonstrated for low-voltage logic application. The boron penetration can effectively be suppressed by the nitrogen implantation technique, even if the gate oxide film is reduced to 2 nm. Moreover the inverter delay with the Al interconnect load can be remarkably improved by the highly drivable MOSFETs with thin gate oxide for low-voltage operation. Furthermore the hot carrier degradation of NMOSFETs can be suppressed as reducing the oxide thickness. However it is found that the hot-carrier degradation of PMOSFETs is enhanced in thin-oxide region under channel hot-hole injection.

Original languageEnglish
Pages (from-to)210-211
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
Publication statusPublished - 1996
Externally publishedYes
EventProceedings of the 1996 Symposium on VLSI Technology - Honolulu, HI, USA
Duration: 1996 Jun 111996 Jun 13

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


Dive into the research topics of 'Sub-quarter-micron dual gate CMOSFETs with ultra-thin gate oxide of 2nm'. Together they form a unique fingerprint.

Cite this