Synchronous ultra-high-density 2RW dual-port 8T-SRAM with circumvention of simultaneous common-row-access

Koji Nii; Yasumasa Tsukamoto; Makoto Yabuuchi; Yasuhiro Masuda; Susumu Imaoka; Keiichi Usui; Shigeki Ohbayashi; Hiroshi Makino; Hirofumi Shinohara

doi:10.1109/JSSC.2009.2013766

Synchronous ultra-high-density 2RW dual-port 8T-SRAM with circumvention of simultaneous common-row-access

Koji Nii^*, Yasumasa Tsukamoto, Makoto Yabuuchi, Yasuhiro Masuda, Susumu Imaoka, Keiichi Usui, Shigeki Ohbayashi, Hiroshi Makino, Hirofumi Shinohara

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

42 Citations (Scopus)

Abstract

We propose an access scheme for a synchronous dual-port (DP) SRAM that minimizes the 8T-DP-cell area and maintains cell stability. A priority row decoder circuit and shifted bitline access scheme eliminates access conflict issues. Using 65 nm CMOS technology (hp90) with the proposed scheme, we fabricated 32 kB DP-SRAM macros. We obtained a 0.71 μm² 8T-DP-cell for which the cell size is only 1.44× larger than a 6T-single-port (SP)-cell. The bit-density of the fabricated 32 kB DP-RAM macro is 667 kbit/mm² , which is 25% larger than a conventional 8T SRAM. The standby leakage is 27% less because of the small drive-NMOS transistor of the proposed 8T-DP-cell.

Original language	English
Article number	4787570
Pages (from-to)	977-986
Number of pages	10
Journal	IEEE Journal of Solid-State Circuits
Volume	44
Issue number	3
DOIs	https://doi.org/10.1109/JSSC.2009.2013766
Publication status	Published - 2009 Mar 1
Externally published	Yes

Keywords

65 nm
CMOS
Dual-port
Embedded SRAM
High density
Low power
Low voltage
Memory
Stability
Two-port
Variability

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/JSSC.2009.2013766

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title = "Synchronous ultra-high-density 2RW dual-port 8T-SRAM with circumvention of simultaneous common-row-access",

abstract = "We propose an access scheme for a synchronous dual-port (DP) SRAM that minimizes the 8T-DP-cell area and maintains cell stability. A priority row decoder circuit and shifted bitline access scheme eliminates access conflict issues. Using 65 nm CMOS technology (hp90) with the proposed scheme, we fabricated 32 kB DP-SRAM macros. We obtained a 0.71 μm2 8T-DP-cell for which the cell size is only 1.44× larger than a 6T-single-port (SP)-cell. The bit-density of the fabricated 32 kB DP-RAM macro is 667 kbit/mm2 , which is 25% larger than a conventional 8T SRAM. The standby leakage is 27% less because of the small drive-NMOS transistor of the proposed 8T-DP-cell.",

keywords = "65 nm, CMOS, Dual-port, Embedded SRAM, High density, Low power, Low voltage, Memory, Stability, Two-port, Variability",

author = "Koji Nii and Yasumasa Tsukamoto and Makoto Yabuuchi and Yasuhiro Masuda and Susumu Imaoka and Keiichi Usui and Shigeki Ohbayashi and Hiroshi Makino and Hirofumi Shinohara",

year = "2009",

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doi = "10.1109/JSSC.2009.2013766",

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AU - Nii, Koji

AU - Tsukamoto, Yasumasa

AU - Yabuuchi, Makoto

AU - Masuda, Yasuhiro

AU - Imaoka, Susumu

AU - Usui, Keiichi

AU - Ohbayashi, Shigeki

AU - Makino, Hiroshi

AU - Shinohara, Hirofumi

PY - 2009/3/1

Y1 - 2009/3/1

N2 - We propose an access scheme for a synchronous dual-port (DP) SRAM that minimizes the 8T-DP-cell area and maintains cell stability. A priority row decoder circuit and shifted bitline access scheme eliminates access conflict issues. Using 65 nm CMOS technology (hp90) with the proposed scheme, we fabricated 32 kB DP-SRAM macros. We obtained a 0.71 μm2 8T-DP-cell for which the cell size is only 1.44× larger than a 6T-single-port (SP)-cell. The bit-density of the fabricated 32 kB DP-RAM macro is 667 kbit/mm2 , which is 25% larger than a conventional 8T SRAM. The standby leakage is 27% less because of the small drive-NMOS transistor of the proposed 8T-DP-cell.

AB - We propose an access scheme for a synchronous dual-port (DP) SRAM that minimizes the 8T-DP-cell area and maintains cell stability. A priority row decoder circuit and shifted bitline access scheme eliminates access conflict issues. Using 65 nm CMOS technology (hp90) with the proposed scheme, we fabricated 32 kB DP-SRAM macros. We obtained a 0.71 μm2 8T-DP-cell for which the cell size is only 1.44× larger than a 6T-single-port (SP)-cell. The bit-density of the fabricated 32 kB DP-RAM macro is 667 kbit/mm2 , which is 25% larger than a conventional 8T SRAM. The standby leakage is 27% less because of the small drive-NMOS transistor of the proposed 8T-DP-cell.

KW - 65 nm

KW - CMOS

KW - Dual-port

KW - Embedded SRAM

KW - High density

KW - Low power

KW - Low voltage

KW - Memory

KW - Stability

KW - Two-port

KW - Variability

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JO - IEEE Journal of Solid-State Circuits

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ER -

Synchronous ultra-high-density 2RW dual-port 8T-SRAM with circumvention of simultaneous common-row-access

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Keywords

ASJC Scopus subject areas

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