System architecture of parallel processing system - Harray

Hayato Yamana, Toshikazu Marushima, Takashi Hagiwara, Yoichi Muraoka

Research output: Chapter in Book/Report/Conference proceedingConference contribution


This paper proposes a parallel processing system - Harray-for scientific computations. Data flow computers are expected to obtain the high performance because they can extract parallelism fully from a program. However, they have many problems, such as the difficulty of controlling the sequence of execution. The - Harray - system is an array processor which adapts two levels of control mechanism; data flow execution in each processor and control flow between processors, in order to take full advantage of both mechanisms. A task which is assigned to a processor is called a "macro-block". Three types of macro-blocking and three types of activation schemes for the macro-block which initiates its execution are introduced in order to attain the high performance. Moreover, a hardware synchronization mechanism is used to reduce synchronization overhead and to gain the liner speedup of the - Harray - system. In this paper, the system architecture of the - Harray - system and its performance evaluation by software simulation are presented.

Original languageEnglish
Title of host publicationProceedings of the 2nd International Conference on Supercomputing, ICS 1988
EditorsJ. Lenfant
PublisherAssociation for Computing Machinery
Number of pages14
ISBN (Electronic)0897912721
Publication statusPublished - 1988 Jun 1
Event2nd International Conference on Supercomputing, ICS 1988 - St. Malo, France
Duration: 1988 Jul 41988 Jul 8

Publication series

NameProceedings of the International Conference on Supercomputing
VolumePart F130184


Other2nd International Conference on Supercomputing, ICS 1988
CitySt. Malo

ASJC Scopus subject areas

  • Computer Science(all)


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