The switching glitch power leakage model

Hongying Liu*, Guoyu Qian, Yukiyasu Tsunoo, Satoshi Goto

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

6 Citations (Scopus)


Power analysis attacks are based on analyzing the power consumption of the cryptographic devices while they perform the encryption operation. Correlation Power Analysis (CPA) attacks exploit the linear relation between the known power consumption and the predicted power consumption of cryptographic devices to recover keys. It has been one of the effective side channel attacks that threaten the security of CMOS circuits. However, few works consider the leakage of glitches at the logic gates. In this paper, we present a new power consumption model, namely Switching Glitch (SG) power leakage model, which not only considers the data dependent switching activities but also including glitch power consumptions in CMOS circuits. Additionally, from a theoretical point of view, we show how to estimate the glitch factor. The experiments against AES implementation validate the proposed model. Compared with CPA based on Hamming Distance model, the power traces of recovering keys have been decreased by as much as 28.9%.

Original languageEnglish
Pages (from-to)1787-1794
Number of pages8
JournalJournal of Software
Issue number9
Publication statusPublished - 2011


  • AES
  • Correlation power analysis (CPA)
  • Glitches
  • Hamming distance
  • Side channel attacks

ASJC Scopus subject areas

  • Software
  • Artificial Intelligence
  • Human-Computer Interaction


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