Thermal-Aware floorplanning for noc-sprinting

Hui Zhu, Cong Hao, Takeshi Yoshimura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)


Due to the rise of utilization wall, a large portion of silicon chips become dark or dim silicon. A NoC-sprinting method is proposed to deal with this problem for instantaneous improvement and the key design constraint of these problems is thermal design power(TDP). In this work we propose a thermalaware Modified Insert After Remove Floorplanning(MD-IARFP) algorithm for NoC-sprinting. Wire length is taken into consideration while only thermal behavior is concerned in the previous work. A thermal model is constructed to evaluate temperature, using relationship between heat transfer and electrical phenomena. Simulated Annealing(SA) based MD-IARFP algorithm is applied to optimize the distribution of active cores. In terms of perturbation of SA, Modified Insert After Remove(MD-IAR) method gives an efficient generation of new floorplan which helps to reduce iterate number and lead to less CPU time. Effective as the experimental results show, our proposal provides better solution with lower temperature and significant decrease of wire length.

Original languageEnglish
Title of host publication2016 IEEE 59th International Midwest Symposium on Circuits and Systems, MWSCAS 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509009169
Publication statusPublished - 2017 Mar 2
Event59th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2016 - Abu Dhabi, United Arab Emirates
Duration: 2016 Oct 162016 Oct 19


Other59th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2016
Country/TerritoryUnited Arab Emirates
CityAbu Dhabi


  • Floorplan
  • Network-on-chip
  • Physical design
  • Thermalaware

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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