Through-silicon-via assignment for 3D ICs

Jianchang Ao; Sheqin Dong; Song Chen; Satoshi Goto

doi:10.1109/ASICON.2011.6157194

Through-silicon-via assignment for 3D ICs

Jianchang Ao^*, Sheqin Dong, Song Chen, Satoshi Goto

^*Corresponding author for this work

Waseda University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Three-dimensional integrated circuits (3D ICs) can alleviate the interconnect problem coming with the decreasing feature size and increasing integration density, and promise a solution to heterogeneous integration. The inter-layer connection, which is generally implemented by the Through-Silicon-Via (TSV), is a key technology for 3D ICs. In this paper, we propose a unified simulated annealing technology to tackle the TSV assignment problem, including the signal TSV assignment of 3D nets and 3D buses. The experiment results show the effective of the method.

Original language	English
Title of host publication	Proceedings of International Conference on ASIC
Pages	353-356
Number of pages	4
DOIs	https://doi.org/10.1109/ASICON.2011.6157194
Publication status	Published - 2011
Event	2011 IEEE 9th International Conference on ASIC, ASICON 2011 - Xiamen Duration: 2011 Oct 25 → 2011 Oct 28

Other

Other	2011 IEEE 9th International Conference on ASIC, ASICON 2011
City	Xiamen
Period	11/10/25 → 11/10/28

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/ASICON.2011.6157194

Cite this

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title = "Through-silicon-via assignment for 3D ICs",

abstract = "Three-dimensional integrated circuits (3D ICs) can alleviate the interconnect problem coming with the decreasing feature size and increasing integration density, and promise a solution to heterogeneous integration. The inter-layer connection, which is generally implemented by the Through-Silicon-Via (TSV), is a key technology for 3D ICs. In this paper, we propose a unified simulated annealing technology to tackle the TSV assignment problem, including the signal TSV assignment of 3D nets and 3D buses. The experiment results show the effective of the method.",

author = "Jianchang Ao and Sheqin Dong and Song Chen and Satoshi Goto",

year = "2011",

doi = "10.1109/ASICON.2011.6157194",

language = "English",

isbn = "9781612841908",

pages = "353--356",

booktitle = "Proceedings of International Conference on ASIC",

note = "2011 IEEE 9th International Conference on ASIC, ASICON 2011 ; Conference date: 25-10-2011 Through 28-10-2011",

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AU - Ao, Jianchang

AU - Dong, Sheqin

AU - Chen, Song

AU - Goto, Satoshi

PY - 2011

Y1 - 2011

N2 - Three-dimensional integrated circuits (3D ICs) can alleviate the interconnect problem coming with the decreasing feature size and increasing integration density, and promise a solution to heterogeneous integration. The inter-layer connection, which is generally implemented by the Through-Silicon-Via (TSV), is a key technology for 3D ICs. In this paper, we propose a unified simulated annealing technology to tackle the TSV assignment problem, including the signal TSV assignment of 3D nets and 3D buses. The experiment results show the effective of the method.

AB - Three-dimensional integrated circuits (3D ICs) can alleviate the interconnect problem coming with the decreasing feature size and increasing integration density, and promise a solution to heterogeneous integration. The inter-layer connection, which is generally implemented by the Through-Silicon-Via (TSV), is a key technology for 3D ICs. In this paper, we propose a unified simulated annealing technology to tackle the TSV assignment problem, including the signal TSV assignment of 3D nets and 3D buses. The experiment results show the effective of the method.

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M3 - Conference contribution

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BT - Proceedings of International Conference on ASIC

T2 - 2011 IEEE 9th International Conference on ASIC, ASICON 2011

Y2 - 25 October 2011 through 28 October 2011

ER -

Through-silicon-via assignment for 3D ICs

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