Through-silicon-via assignment for 3D ICs

Jianchang Ao*, Sheqin Dong, Song Chen, Satoshi Goto

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Three-dimensional integrated circuits (3D ICs) can alleviate the interconnect problem coming with the decreasing feature size and increasing integration density, and promise a solution to heterogeneous integration. The inter-layer connection, which is generally implemented by the Through-Silicon-Via (TSV), is a key technology for 3D ICs. In this paper, we propose a unified simulated annealing technology to tackle the TSV assignment problem, including the signal TSV assignment of 3D nets and 3D buses. The experiment results show the effective of the method.

Original languageEnglish
Title of host publicationProceedings of International Conference on ASIC
Number of pages4
Publication statusPublished - 2011
Event2011 IEEE 9th International Conference on ASIC, ASICON 2011 - Xiamen
Duration: 2011 Oct 252011 Oct 28


Other2011 IEEE 9th International Conference on ASIC, ASICON 2011

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering


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