Throughput driven check point selection in suspicious timing error prediction based designs

Hiroaki Igarashi; Youhua Shi; Masao Yanagisawa; Nozomu Togawa

doi:10.1109/LASCAS.2014.6820280

Throughput driven check point selection in suspicious timing error prediction based designs

Hiroaki Igarashi, Youhua Shi, Masao Yanagisawa, Nozomu Togawa

School of Fundamental Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this paper, a throughput-driven design technique is proposed, in which a suspicious timing error prediction circuit is inserted to monitor the signal transitions at some selected check points. Unlike previous works where timing errors are detected after their occurrence, the proposed method tries to use the real intermediate signal transitions for timing error prediction. The check point selection will affect both the maximal operation frequency and the suspicious timing error overestimation rate, both of which have an effect on the overall throughput, thus an analysis on the check point selection is also given. In our work, the circuit can be overclocked by a factor of 2 or more with ignorable area overhead while guarantees the always-correct output.

Original language	English
Title of host publication	2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings
Publisher	IEEE Computer Society
ISBN (Print)	9781479925070
DOIs	https://doi.org/10.1109/LASCAS.2014.6820280
Publication status	Published - 2014 Jan 1
Event	2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Santiago, Chile Duration: 2014 Feb 25 → 2014 Feb 28

Publication series

Name	2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings

Conference

Conference	2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014
Country/Territory	Chile
City	Santiago
Period	14/2/25 → 14/2/28

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/LASCAS.2014.6820280

Cite this

Igarashi, H., Shi, Y., Yanagisawa, M., & Togawa, N. (2014). Throughput driven check point selection in suspicious timing error prediction based designs. In 2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings Article 6820280 (2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings). IEEE Computer Society. https://doi.org/10.1109/LASCAS.2014.6820280

Throughput driven check point selection in suspicious timing error prediction based designs. / Igarashi, Hiroaki; Shi, Youhua ; Yanagisawa, Masao et al.
2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings. IEEE Computer Society, 2014. 6820280 (2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Igarashi, H, Shi, Y , Yanagisawa, M & Togawa, N 2014, Throughput driven check point selection in suspicious timing error prediction based designs. in 2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings., 6820280, 2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings, IEEE Computer Society, 2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014, Santiago, Chile, 14/2/25. https://doi.org/10.1109/LASCAS.2014.6820280

Igarashi H, Shi Y , Yanagisawa M , Togawa N. Throughput driven check point selection in suspicious timing error prediction based designs. In 2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings. IEEE Computer Society. 2014. 6820280. (2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings). doi: 10.1109/LASCAS.2014.6820280

Igarashi, Hiroaki ; Shi, Youhua ; Yanagisawa, Masao et al. / Throughput driven check point selection in suspicious timing error prediction based designs. 2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings. IEEE Computer Society, 2014. (2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings).

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AB - In this paper, a throughput-driven design technique is proposed, in which a suspicious timing error prediction circuit is inserted to monitor the signal transitions at some selected check points. Unlike previous works where timing errors are detected after their occurrence, the proposed method tries to use the real intermediate signal transitions for timing error prediction. The check point selection will affect both the maximal operation frequency and the suspicious timing error overestimation rate, both of which have an effect on the overall throughput, thus an analysis on the check point selection is also given. In our work, the circuit can be overclocked by a factor of 2 or more with ignorable area overhead while guarantees the always-correct output.

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Throughput driven check point selection in suspicious timing error prediction based designs

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