SAT-based exact synthesis has important applications in logic optimization problems, and its scalability and computational speed greatly affect the optimization results. In the paper, a new topological constraint using the list of levels of inputs of each gate is introduced and accelerates the exact synthesis. Such topological constraints can reduce the search space by structure enumeration. By our new partition of the synthesis problem, we can maintain a good balance between runtime on a single satisfiability problem and the number of satisfiability problems. When compared to the fence-based method and the partial DAG based method, our methodology demonstrates a considerable reduction in runtime of 24.5% and 5.7%, respectively. Furthermore, our implementation can extend the scalability of SAT-based exact synthesis.
|Title of host publication
|IEEE International Symposium on Circuits and Systems, ISCAS 2022
|Institute of Electrical and Electronics Engineers Inc.
|Number of pages
|Published - 2022
|2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022 - Austin, United States
Duration: 2022 May 27 → 2022 Jun 1
|Proceedings - IEEE International Symposium on Circuits and Systems
|2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022
|22/5/27 → 22/6/1
- Logic synthesis
- Majority synthesis
- Majority-Inverter Graph
ASJC Scopus subject areas
- Electrical and Electronic Engineering