Topology optimization of conductors in electrical circuit

Katsuya Nomura*, Shintaro Yamasaki, Kentaro Yaji, Hiroki Bo, Atsuhiro Takahashi, Takashi Kojima, Kikuo Fujita

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

11 Citations (Scopus)


This study proposes a topology optimization method for realizing a free-form design of conductors in electrical circuits. Conductors in a circuit must connect components, such as voltage sources, resistors, capacitors, and inductors, according to the given circuit diagram. The shape of conductors has a strong effect on the high-frequency performance of a circuit due to parasitic circuit elements such as parasitic inductance and capacitance. In this study, we apply topology optimization to the design of such conductors to minimize parasitic effects with maximum flexibility of shape manipulation. However, when the distribution of conductors is repeatedly updated in topology optimization, disconnections and connections of conductors that cause open and short circuits, respectively, may occur. To prevent this, a method that uses fictitious electric current and electric field calculations is proposed. Disallowed disconnections are prevented by limiting the maximum value of the fictitious current density in conductors where a current is induced. This concept is based on the fact that an electric current becomes concentrated in a thin conductor before disconnection occurs. Disallowed connections are prevented by limiting the maximum value of the fictitious electric field strength around conductors where a voltage is applied. This is based on the fact that the electric field in a parallel plate capacitor is inversely proportional to the distance between the plates. These limitations are aggregated as a single constraint using the Kreisselmeier-Steinhauser function in the formulation of optimization problems. This constraint prevents only disallowed disconnections and connections, but does not prevent allowed topology changes. The effectiveness of the constraint is confirmed using simple examples, and an actual design problem involving conductors in electromagnetic interference filters is used to verify that the proposed constraint can be utilized for conductor optimization.

Original languageEnglish
Pages (from-to)2205-2225
Number of pages21
JournalStructural and Multidisciplinary Optimization
Issue number6
Publication statusPublished - 2019 Jun 15
Externally publishedYes


  • Conductor
  • Electrical circuit
  • Electromagnetic interference filter
  • Geometric constraint
  • Topology optimization

ASJC Scopus subject areas

  • Software
  • Control and Systems Engineering
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Control and Optimization


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