Ultra-high-speed and low-power SOI CMOS technology with body-tied hybrid trench isolation structure

Yuuichi Hirano; Takashi Ipposhi; Dang Hai Thai; Toshiaki Iwamatsu; Tatsuhiko Ikeda; Mikio Tsujiuchi; Shigeto Maegawa; Masahide Inuishi; Yuzuru Ohji

Ultra-high-speed and low-power SOI CMOS technology with body-tied hybrid trench isolation structure

Yuuichi Hirano^*, Takashi Ipposhi, Dang Hai Thai, Toshiaki Iwamatsu, Tatsuhiko Ikeda, Mikio Tsujiuchi, Shigeto Maegawa, Masahide Inuishi, Yuzuru Ohji

^*Corresponding author for this work

Research output: Contribution to conference › Paper › peer-review

Abstract

The hybrid-trench-isolation (HTI) SOI technology overcomes the scaling limitations caused by the difficulty of the gate thinning. A high-speed and low-power microcontroller including logic, memory, analog, and PLL circuits has been demonstrated by using the HTI SOI technology with bulk-layout compatibility. Over 10Gbps and low-noise operation with excellent eye patterns of output buffer circuits were also obtained for ultra-high-speed network LSIs. It is also verified that low-voltage and high-speed operation is achieved for an Actively Body-bias Controlled (ABC) SOI SRAM that has a new cell structure connecting the bodies of the access and the driver transistors with the word line. It is concluded that the SOI technology with the HTI structure is one of the solutions against the scaling limitations.

Original language	English
Pages	60-64
Number of pages	5
Publication status	Published - 2004
Externally published	Yes
Event	Dielectrics for Nanosystems: Materials Science, Processing, Reliability, and Manufacturing - Proceedings of the First International Symposium - Honolulu, HI, United States Duration: 2004 Oct 3 → 2004 Oct 8

Other

Other	Dielectrics for Nanosystems: Materials Science, Processing, Reliability, and Manufacturing - Proceedings of the First International Symposium
Country/Territory	United States
City	Honolulu, HI
Period	04/10/3 → 04/10/8

ASJC Scopus subject areas

Engineering(all)

Cite this

Hirano, Y., Ipposhi, T., Thai, D. H., Iwamatsu, T., Ikeda, T., Tsujiuchi, M., Maegawa, S., Inuishi, M., & Ohji, Y. (2004). Ultra-high-speed and low-power SOI CMOS technology with body-tied hybrid trench isolation structure. 60-64. Paper presented at Dielectrics for Nanosystems: Materials Science, Processing, Reliability, and Manufacturing - Proceedings of the First International Symposium, Honolulu, HI, United States.

Ultra-high-speed and low-power SOI CMOS technology with body-tied hybrid trench isolation structure. / Hirano, Yuuichi; Ipposhi, Takashi; Thai, Dang Hai et al.
2004. 60-64 Paper presented at Dielectrics for Nanosystems: Materials Science, Processing, Reliability, and Manufacturing - Proceedings of the First International Symposium, Honolulu, HI, United States.

Research output: Contribution to conference › Paper › peer-review

Hirano, Y, Ipposhi, T, Thai, DH, Iwamatsu, T, Ikeda, T, Tsujiuchi, M, Maegawa, S, Inuishi, M & Ohji, Y 2004, 'Ultra-high-speed and low-power SOI CMOS technology with body-tied hybrid trench isolation structure', Paper presented at Dielectrics for Nanosystems: Materials Science, Processing, Reliability, and Manufacturing - Proceedings of the First International Symposium, Honolulu, HI, United States, 04/10/3 - 04/10/8 pp. 60-64.

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abstract = "The hybrid-trench-isolation (HTI) SOI technology overcomes the scaling limitations caused by the difficulty of the gate thinning. A high-speed and low-power microcontroller including logic, memory, analog, and PLL circuits has been demonstrated by using the HTI SOI technology with bulk-layout compatibility. Over 10Gbps and low-noise operation with excellent eye patterns of output buffer circuits were also obtained for ultra-high-speed network LSIs. It is also verified that low-voltage and high-speed operation is achieved for an Actively Body-bias Controlled (ABC) SOI SRAM that has a new cell structure connecting the bodies of the access and the driver transistors with the word line. It is concluded that the SOI technology with the HTI structure is one of the solutions against the scaling limitations.",

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AU - Hirano, Yuuichi

AU - Ipposhi, Takashi

AU - Thai, Dang Hai

AU - Iwamatsu, Toshiaki

AU - Ikeda, Tatsuhiko

AU - Tsujiuchi, Mikio

AU - Maegawa, Shigeto

AU - Inuishi, Masahide

AU - Ohji, Yuzuru

PY - 2004

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N2 - The hybrid-trench-isolation (HTI) SOI technology overcomes the scaling limitations caused by the difficulty of the gate thinning. A high-speed and low-power microcontroller including logic, memory, analog, and PLL circuits has been demonstrated by using the HTI SOI technology with bulk-layout compatibility. Over 10Gbps and low-noise operation with excellent eye patterns of output buffer circuits were also obtained for ultra-high-speed network LSIs. It is also verified that low-voltage and high-speed operation is achieved for an Actively Body-bias Controlled (ABC) SOI SRAM that has a new cell structure connecting the bodies of the access and the driver transistors with the word line. It is concluded that the SOI technology with the HTI structure is one of the solutions against the scaling limitations.

AB - The hybrid-trench-isolation (HTI) SOI technology overcomes the scaling limitations caused by the difficulty of the gate thinning. A high-speed and low-power microcontroller including logic, memory, analog, and PLL circuits has been demonstrated by using the HTI SOI technology with bulk-layout compatibility. Over 10Gbps and low-noise operation with excellent eye patterns of output buffer circuits were also obtained for ultra-high-speed network LSIs. It is also verified that low-voltage and high-speed operation is achieved for an Actively Body-bias Controlled (ABC) SOI SRAM that has a new cell structure connecting the bodies of the access and the driver transistors with the word line. It is concluded that the SOI technology with the HTI structure is one of the solutions against the scaling limitations.

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Ultra-high-speed and low-power SOI CMOS technology with body-tied hybrid trench isolation structure

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