Ultra low power QC-LDPC decoder with high parallelism

Ying Cui; Xiao Peng; Zhixiang Chen; Xiongxin Zhao; Yichao Lu; Dajiang Zhou; Satoshi Goto

doi:10.1109/SOCC.2011.6085136

Ultra low power QC-LDPC decoder with high parallelism

Ying Cui^*, Xiao Peng, Zhixiang Chen, Xiongxin Zhao, Yichao Lu, Dajiang Zhou, Satoshi Goto

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

9 Citations (Scopus)

Abstract

This paper presents a novel high parallel decoder architecture for the quasi-cyclic low-density parity-check (QC-LDPC) codes defined in WiMAX system. Based on the turbo-decoding message passing (TDMP) algorithm, this architecture costs 816 clock cycles for each iteration in the decoding process. In the normalized comparison with the state-of-art work, this design achieves up to 6.5 higher parallelism and 76% power reduction. The energy/bit/iteration of this design is only 1/5 of the previous work.

Original language	English
Title of host publication	International System on Chip Conference
Pages	142-145
Number of pages	4
DOIs	https://doi.org/10.1109/SOCC.2011.6085136
Publication status	Published - 2011
Event	24th IEEE International System on Chip Conference, SOCC 2011 - Taipei Duration: 2011 Sept 26 → 2011 Sept 28

Other

Other	24th IEEE International System on Chip Conference, SOCC 2011
City	Taipei
Period	11/9/26 → 11/9/28

ASJC Scopus subject areas

Hardware and Architecture
Control and Systems Engineering
Electrical and Electronic Engineering

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10.1109/SOCC.2011.6085136

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title = "Ultra low power QC-LDPC decoder with high parallelism",

abstract = "This paper presents a novel high parallel decoder architecture for the quasi-cyclic low-density parity-check (QC-LDPC) codes defined in WiMAX system. Based on the turbo-decoding message passing (TDMP) algorithm, this architecture costs 816 clock cycles for each iteration in the decoding process. In the normalized comparison with the state-of-art work, this design achieves up to 6.5 higher parallelism and 76% power reduction. The energy/bit/iteration of this design is only 1/5 of the previous work.",

author = "Ying Cui and Xiao Peng and Zhixiang Chen and Xiongxin Zhao and Yichao Lu and Dajiang Zhou and Satoshi Goto",

year = "2011",

doi = "10.1109/SOCC.2011.6085136",

language = "English",

isbn = "9781457716164",

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booktitle = "International System on Chip Conference",

note = "24th IEEE International System on Chip Conference, SOCC 2011 ; Conference date: 26-09-2011 Through 28-09-2011",

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AU - Cui, Ying

AU - Peng, Xiao

AU - Chen, Zhixiang

AU - Zhao, Xiongxin

AU - Lu, Yichao

AU - Zhou, Dajiang

AU - Goto, Satoshi

PY - 2011

Y1 - 2011

N2 - This paper presents a novel high parallel decoder architecture for the quasi-cyclic low-density parity-check (QC-LDPC) codes defined in WiMAX system. Based on the turbo-decoding message passing (TDMP) algorithm, this architecture costs 816 clock cycles for each iteration in the decoding process. In the normalized comparison with the state-of-art work, this design achieves up to 6.5 higher parallelism and 76% power reduction. The energy/bit/iteration of this design is only 1/5 of the previous work.

AB - This paper presents a novel high parallel decoder architecture for the quasi-cyclic low-density parity-check (QC-LDPC) codes defined in WiMAX system. Based on the turbo-decoding message passing (TDMP) algorithm, this architecture costs 816 clock cycles for each iteration in the decoding process. In the normalized comparison with the state-of-art work, this design achieves up to 6.5 higher parallelism and 76% power reduction. The energy/bit/iteration of this design is only 1/5 of the previous work.

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DO - 10.1109/SOCC.2011.6085136

M3 - Conference contribution

AN - SCOPUS:84255194435

SN - 9781457716164

SP - 142

EP - 145

BT - International System on Chip Conference

T2 - 24th IEEE International System on Chip Conference, SOCC 2011

Y2 - 26 September 2011 through 28 September 2011

ER -

Ultra low power QC-LDPC decoder with high parallelism

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