VIDEO SIGNAL PROCESSING LSI AND ITS APPLICATION TO TV CODEC.

Shin ichi Maki; Kiichi Matsuda; Toshitaka Tsuda; Hirokazu Fukui; Hiroshisa Gambe

VIDEO SIGNAL PROCESSING LSI AND ITS APPLICATION TO TV CODEC.

Shin ichi Maki^*, Kiichi Matsuda, Toshitaka Tsuda, Hirokazu Fukui, Hiroshisa Gambe

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

Abstract

The authors describe an LSI that was developed for wide application in digital video signal processing. The LSI consists of two independent 12-bit full adder/subtracters and a variable delay unit. The minimum arithmetic operation cycle time is 67 ns and the power dissipation is 250 mW. The LSI is packaged in a 135-pin RIT package. It has a rather simple structure, but has very powerful applications in real-time video signal processing. The application of this LSI to a TV conferencing codec is presented.

Original language	English
Pages (from-to)	809-812
Number of pages	4
Journal	Unknown Journal
Publication status	Published - 1986

ASJC Scopus subject areas

Signal Processing
Electrical and Electronic Engineering
Acoustics and Ultrasonics

Cite this

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title = "VIDEO SIGNAL PROCESSING LSI AND ITS APPLICATION TO TV CODEC.",

abstract = "The authors describe an LSI that was developed for wide application in digital video signal processing. The LSI consists of two independent 12-bit full adder/subtracters and a variable delay unit. The minimum arithmetic operation cycle time is 67 ns and the power dissipation is 250 mW. The LSI is packaged in a 135-pin RIT package. It has a rather simple structure, but has very powerful applications in real-time video signal processing. The application of this LSI to a TV conferencing codec is presented.",

author = "Maki, {Shin ichi} and Kiichi Matsuda and Toshitaka Tsuda and Hirokazu Fukui and Hiroshisa Gambe",

year = "1986",

language = "English",

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journal = "Nuclear Physics A",

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AU - Matsuda, Kiichi

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AU - Fukui, Hirokazu

AU - Gambe, Hiroshisa

PY - 1986

Y1 - 1986

N2 - The authors describe an LSI that was developed for wide application in digital video signal processing. The LSI consists of two independent 12-bit full adder/subtracters and a variable delay unit. The minimum arithmetic operation cycle time is 67 ns and the power dissipation is 250 mW. The LSI is packaged in a 135-pin RIT package. It has a rather simple structure, but has very powerful applications in real-time video signal processing. The application of this LSI to a TV conferencing codec is presented.

AB - The authors describe an LSI that was developed for wide application in digital video signal processing. The LSI consists of two independent 12-bit full adder/subtracters and a variable delay unit. The minimum arithmetic operation cycle time is 67 ns and the power dissipation is 250 mW. The LSI is packaged in a 135-pin RIT package. It has a rather simple structure, but has very powerful applications in real-time video signal processing. The application of this LSI to a TV conferencing codec is presented.

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VIDEO SIGNAL PROCESSING LSI AND ITS APPLICATION TO TV CODEC.

Abstract

ASJC Scopus subject areas

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