Abstract
A system for quick VLSI architecture evaluation is proposed. It consists of a simple hardware description language, a simulator, and a synthesizer. The authors claim that by using this system, the designer can make sure of his architecture's design adequacy in a very short time.
| Original language | English |
|---|---|
| Title of host publication | Unknown Host Publication Title |
| Place of Publication | New York, NY, USA |
| Publisher | IEEE |
| Pages | 60-63 |
| Number of pages | 4 |
| ISBN (Print) | 0818607351 |
| Publication status | Published - 1986 |
| Externally published | Yes |
ASJC Scopus subject areas
- Engineering(all)