VLSI architecture of a low complexity face detection algorithm for real-time video encoding

Tianruo Zhang; Minghui Wang; Chen Liu; Satoshi Goto

doi:10.1109/ASICON.2009.5351587

VLSI architecture of a low complexity face detection algorithm for real-time video encoding

Tianruo Zhang^*, Minghui Wang, Chen Liu, Satoshi Goto

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Combining video encoder and content analyzer to improve the encoding efficiency by content-aware algorithms is very challenging now. For the aiming application of low cost hardware real-time encoder with face detectionfor videophone, this paper proposes a face detection algorithm to detect each macroblock (MB) as one part of a face or not. This face detection algorithm has a unique estimation-and-verification process and can be combined with a H264 encoder by MB level pipeline architecture. 97.91% MBs in faces can be detected. VLSl architecture of proposed face detection algorithm is designed and an area of 4.3k gates is achieved. Power consumption is only 1.45mW at 100MHz. The detection speed achieves 1315fps in ClF sequences.

Original language	English
Title of host publication	ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC
Pages	147-150
Number of pages	4
DOIs	https://doi.org/10.1109/ASICON.2009.5351587
Publication status	Published - 2009
Event	2009 8th IEEE International Conference on ASIC, ASICON 2009 - Changsha Duration: 2009 Oct 20 → 2009 Oct 23

Other

Other	2009 8th IEEE International Conference on ASIC, ASICON 2009
City	Changsha
Period	09/10/20 → 09/10/23

Keywords

Face detection
VLSI architecture

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ASICON.2009.5351587

Cite this

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title = "VLSI architecture of a low complexity face detection algorithm for real-time video encoding",

abstract = "Combining video encoder and content analyzer to improve the encoding efficiency by content-aware algorithms is very challenging now. For the aiming application of low cost hardware real-time encoder with face detectionfor videophone, this paper proposes a face detection algorithm to detect each macroblock (MB) as one part of a face or not. This face detection algorithm has a unique estimation-and-verification process and can be combined with a H264 encoder by MB level pipeline architecture. 97.91% MBs in faces can be detected. VLSl architecture of proposed face detection algorithm is designed and an area of 4.3k gates is achieved. Power consumption is only 1.45mW at 100MHz. The detection speed achieves 1315fps in ClF sequences.",

keywords = "Face detection, VLSI architecture",

author = "Tianruo Zhang and Minghui Wang and Chen Liu and Satoshi Goto",

year = "2009",

doi = "10.1109/ASICON.2009.5351587",

language = "English",

isbn = "9781424438686",

pages = "147--150",

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note = "2009 8th IEEE International Conference on ASIC, ASICON 2009 ; Conference date: 20-10-2009 Through 23-10-2009",

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T1 - VLSI architecture of a low complexity face detection algorithm for real-time video encoding

AU - Zhang, Tianruo

AU - Wang, Minghui

AU - Liu, Chen

AU - Goto, Satoshi

PY - 2009

Y1 - 2009

N2 - Combining video encoder and content analyzer to improve the encoding efficiency by content-aware algorithms is very challenging now. For the aiming application of low cost hardware real-time encoder with face detectionfor videophone, this paper proposes a face detection algorithm to detect each macroblock (MB) as one part of a face or not. This face detection algorithm has a unique estimation-and-verification process and can be combined with a H264 encoder by MB level pipeline architecture. 97.91% MBs in faces can be detected. VLSl architecture of proposed face detection algorithm is designed and an area of 4.3k gates is achieved. Power consumption is only 1.45mW at 100MHz. The detection speed achieves 1315fps in ClF sequences.

AB - Combining video encoder and content analyzer to improve the encoding efficiency by content-aware algorithms is very challenging now. For the aiming application of low cost hardware real-time encoder with face detectionfor videophone, this paper proposes a face detection algorithm to detect each macroblock (MB) as one part of a face or not. This face detection algorithm has a unique estimation-and-verification process and can be combined with a H264 encoder by MB level pipeline architecture. 97.91% MBs in faces can be detected. VLSl architecture of proposed face detection algorithm is designed and an area of 4.3k gates is achieved. Power consumption is only 1.45mW at 100MHz. The detection speed achieves 1315fps in ClF sequences.

KW - Face detection

KW - VLSI architecture

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AN - SCOPUS:77949366410

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EP - 150

BT - ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC

T2 - 2009 8th IEEE International Conference on ASIC, ASICON 2009

Y2 - 20 October 2009 through 23 October 2009

ER -

VLSI architecture of a low complexity face detection algorithm for real-time video encoding

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Keywords

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