VLSI architecture of HEVC intra prediction for 8K UHDTV applications

Jianbin Zhou; Dajiang Zhou; Heming Sun; Satoshi Goto

doi:10.1109/ICIP.2014.7025254

VLSI architecture of HEVC intra prediction for 8K UHDTV applications

Jianbin Zhou, Dajiang Zhou, Heming Sun, Satoshi Goto

Waseda Research Institute for Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

8 Citations (Scopus)

Abstract

This paper presents an efficient VLSI architecture of intra prediction for 8K×4K HEVC decoder. It supports all 35 intra prediction modes and prediction sizes ranging from 4×4 to 64×64. This works proposed a Cyclic SRAM Banks based Parallel Reference Sample Fetching (CSB-PRSF), which guarantees enough reference samples for prediction and reduces the number of registers used for storing reference samples. To guarantee high throughput, 16 pixels are predicted by 4×4 Block Based Pipelining, and dependency between neighboring blocks is eliminated by Hybrid Data Forwarding and Block Reordering. This architecture is synthesized using 90nm technology and the maximum working frequency is 469 MHz, with 72.1K gates area. Running at 397MHz, the architecture can support 4320p@120fps HEVC intra decoding, with full modes and full sizes.

Original language	English
Title of host publication	2014 IEEE International Conference on Image Processing, ICIP 2014
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1273-1277
Number of pages	5
ISBN (Electronic)	9781479957514
DOIs	https://doi.org/10.1109/ICIP.2014.7025254
Publication status	Published - 2014 Jan 28

Publication series

Name	2014 IEEE International Conference on Image Processing, ICIP 2014

Keywords

8K UDTV
HEVC decoder
VLSI architecture
intra prediction

ASJC Scopus subject areas

Computer Vision and Pattern Recognition

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10.1109/ICIP.2014.7025254

Cite this

Zhou, J., Zhou, D., Sun, H., & Goto, S. (2014). VLSI architecture of HEVC intra prediction for 8K UHDTV applications. In 2014 IEEE International Conference on Image Processing, ICIP 2014 (pp. 1273-1277). Article 7025254 (2014 IEEE International Conference on Image Processing, ICIP 2014). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICIP.2014.7025254

VLSI architecture of HEVC intra prediction for 8K UHDTV applications. / Zhou, Jianbin; Zhou, Dajiang; Sun, Heming et al.
2014 IEEE International Conference on Image Processing, ICIP 2014. Institute of Electrical and Electronics Engineers Inc., 2014. p. 1273-1277 7025254 (2014 IEEE International Conference on Image Processing, ICIP 2014).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Zhou, J, Zhou, D, Sun, H & Goto, S 2014, VLSI architecture of HEVC intra prediction for 8K UHDTV applications. in 2014 IEEE International Conference on Image Processing, ICIP 2014., 7025254, 2014 IEEE International Conference on Image Processing, ICIP 2014, Institute of Electrical and Electronics Engineers Inc., pp. 1273-1277. https://doi.org/10.1109/ICIP.2014.7025254

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VLSI architecture of HEVC intra prediction for 8K UHDTV applications

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