VLSI chip set for a small mainframe processor.

S. Yamada; T. Sano; M. Saito; M. Motohashi; H. Oki; H. Tsuruya

VLSI chip set for a small mainframe processor.

S. Yamada^*, T. Sano, M. Saito, M. Motohashi, H. Oki, H. Tsuruya

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

1 Citation (Scopus)

Abstract

A CMOS VLSI chip set, which consists of three chips including a chip with 495,000 transistors, 0.8-ns gate delay, and a 12-ns RAM, has been developed to achieve a high-performance 32-bit mainframe processor. This chip set uses a 1.2-μm double-diffused-drain transistor, double-layer metallization technology and a sophisticated CAD (computer-aided design) system. Each chip is mounted on a 288-pin surface-mount pin grid array package. A one-board CPU can be realized by assembling the chip set on a multilayer printed wiring board with RAMs and interface LSIs.

Original language	English
Pages (from-to)	24.6/1-4
Journal	Proceedings of the Custom Integrated Circuits Conference
Publication status	Published - 1988
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

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title = "VLSI chip set for a small mainframe processor.",

abstract = "A CMOS VLSI chip set, which consists of three chips including a chip with 495,000 transistors, 0.8-ns gate delay, and a 12-ns RAM, has been developed to achieve a high-performance 32-bit mainframe processor. This chip set uses a 1.2-μm double-diffused-drain transistor, double-layer metallization technology and a sophisticated CAD (computer-aided design) system. Each chip is mounted on a 288-pin surface-mount pin grid array package. A one-board CPU can be realized by assembling the chip set on a multilayer printed wiring board with RAMs and interface LSIs.",

author = "S. Yamada and T. Sano and M. Saito and M. Motohashi and H. Oki and H. Tsuruya",

year = "1988",

language = "English",

pages = "24.6/1--4",

journal = "Proceedings of the Custom Integrated Circuits Conference",

issn = "0886-5930",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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T1 - VLSI chip set for a small mainframe processor.

AU - Yamada, S.

AU - Sano, T.

AU - Saito, M.

AU - Motohashi, M.

AU - Oki, H.

AU - Tsuruya, H.

PY - 1988

Y1 - 1988

N2 - A CMOS VLSI chip set, which consists of three chips including a chip with 495,000 transistors, 0.8-ns gate delay, and a 12-ns RAM, has been developed to achieve a high-performance 32-bit mainframe processor. This chip set uses a 1.2-μm double-diffused-drain transistor, double-layer metallization technology and a sophisticated CAD (computer-aided design) system. Each chip is mounted on a 288-pin surface-mount pin grid array package. A one-board CPU can be realized by assembling the chip set on a multilayer printed wiring board with RAMs and interface LSIs.

AB - A CMOS VLSI chip set, which consists of three chips including a chip with 495,000 transistors, 0.8-ns gate delay, and a 12-ns RAM, has been developed to achieve a high-performance 32-bit mainframe processor. This chip set uses a 1.2-μm double-diffused-drain transistor, double-layer metallization technology and a sophisticated CAD (computer-aided design) system. Each chip is mounted on a 288-pin surface-mount pin grid array package. A one-board CPU can be realized by assembling the chip set on a multilayer printed wiring board with RAMs and interface LSIs.

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M3 - Conference article

AN - SCOPUS:0024134555

SN - 0886-5930

SP - 24.6/1-4

JO - Proceedings of the Custom Integrated Circuits Conference

JF - Proceedings of the Custom Integrated Circuits Conference

ER -

VLSI chip set for a small mainframe processor.

Abstract

ASJC Scopus subject areas

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