W-polymetal gate with low W/poly-Si interface resistance for high-speed/high-density embedded memory

Tomohiro Yamashita*, Yukio Nishida, Kiyoshi Hayashi, Takahisa Eimori, Masahide Inuishi, Yuzuru Ohji

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

13 Citations (Scopus)


A new W-polymetal gate electrode with the structure of W/WN/WSi/poly-Si is proposed. The W-polymetal gate is suitable for high-density memories since it has low resistance and is compatible with the self-aligned contact process. In our study, however, it is found that the interface of W and poly-Si has non-ohmic and quite high resistance in the case wherein only WN is used as a barrier film. This resistance increases the delay in complementary metal-oxide-semiconductor (CMOS) logic circuits and prevents high-speed operation. Our new process includes the deposition of thin WSi on poly-Si, followed by rapid thermal annealing, which results in ohmic and sufficiently low contact resistance between W and poly-Si. It is also demonstrated that selective gate reoxidation is successfully applied for this new structure, and the insertion of thin WSi does not cause any adverse effect on the electrical characteristics of metal-oxide-semiconductor field-effect transistor (MOSFET). This process is promising for high-speed and high-density embedded memory.

Original languageEnglish
Pages (from-to)1799-1803
Number of pages5
JournalJapanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
Issue number4 B
Publication statusPublished - 2004 Apr
Externally publishedYes


  • Polymetal gate
  • Silicon
  • Tungsten nitride
  • Tungsten silicide

ASJC Scopus subject areas

  • General Engineering
  • General Physics and Astronomy


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