Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability

Yasumasa Tsukamoto; Koji Nii; Susumu Imaoka; Yuji Oda; Shigeki Ohbayashi; Tomoaki Yoshizawa; Hiroshi Makino; Koichiro Ishibashi; Hirofumi Shinohara

doi:10.1109/ICCAD.2005.1560101

Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability

Yasumasa Tsukamoto^*, Koji Nii, Susumu Imaoka, Yuji Oda, Shigeki Ohbayashi, Tomoaki Yoshizawa, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

49 Citations (Scopus)

Abstract

6T-SRAM cells in the sub-100 nm CMOS generation are now being exposed to a fatal risk that originates from large local Vth variability (σ _{V_Local}). To achieve high-yield SRAM arrays in presence of random σ_{V_Local} component, we propose worst-case analysis that determines the boundary of the stable Vth region for the SRAM read/write DC margin (Vth curve). Applying this to our original 65 nm SPICE model, we demonstrate typical behavior of the Vth curve and show new criteria for discussing SRAM array stability with Vth variability.

Original language	English
Title of host publication	Proceedings of theICCAD-2005
Subtitle of host publication	International Conference on Computer-Aided Design
Pages	398-405
Number of pages	8
DOIs	https://doi.org/10.1109/ICCAD.2005.1560101
Publication status	Published - 2005
Externally published	Yes
Event	ICCAD-2005: IEEE/ACM International Conference on Computer-Aided Design, 2005 - San Jose, CA, United States Duration: 2005 Nov 6 → 2005 Nov 10

Publication series

Name	IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
Volume	2005
ISSN (Print)	1092-3152

Other

Other	ICCAD-2005: IEEE/ACM International Conference on Computer-Aided Design, 2005
Country/Territory	United States
City	San Jose, CA
Period	05/11/6 → 05/11/10

Keywords

Design form manufacturability (DFM)
Local Vth variability
SRAM
Static noise margin

ASJC Scopus subject areas

Software
Computer Science Applications
Computer Graphics and Computer-Aided Design

Access to Document

10.1109/ICCAD.2005.1560101

Cite this

Tsukamoto, Y., Nii, K., Imaoka, S., Oda, Y., Ohbayashi, S., Yoshizawa, T., Makino, H., Ishibashi, K., & Shinohara, H. (2005). Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability. In Proceedings of theICCAD-2005: International Conference on Computer-Aided Design (pp. 398-405). Article 1560101 (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD; Vol. 2005). https://doi.org/10.1109/ICCAD.2005.1560101

Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability. / Tsukamoto, Yasumasa; Nii, Koji; Imaoka, Susumu et al.
Proceedings of theICCAD-2005: International Conference on Computer-Aided Design. 2005. p. 398-405 1560101 (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD; Vol. 2005).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Tsukamoto, Y, Nii, K, Imaoka, S, Oda, Y, Ohbayashi, S, Yoshizawa, T, Makino, H, Ishibashi, K & Shinohara, H 2005, Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability. in Proceedings of theICCAD-2005: International Conference on Computer-Aided Design., 1560101, IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, vol. 2005, pp. 398-405, ICCAD-2005: IEEE/ACM International Conference on Computer-Aided Design, 2005, San Jose, CA, United States, 05/11/6. https://doi.org/10.1109/ICCAD.2005.1560101

Tsukamoto Y, Nii K, Imaoka S, Oda Y, Ohbayashi S, Yoshizawa T et al. Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability. In Proceedings of theICCAD-2005: International Conference on Computer-Aided Design. 2005. p. 398-405. 1560101. (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD). doi: 10.1109/ICCAD.2005.1560101

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abstract = "6T-SRAM cells in the sub-100 nm CMOS generation are now being exposed to a fatal risk that originates from large local Vth variability (σ V_Local). To achieve high-yield SRAM arrays in presence of random σV_Local component, we propose worst-case analysis that determines the boundary of the stable Vth region for the SRAM read/write DC margin (Vth curve). Applying this to our original 65 nm SPICE model, we demonstrate typical behavior of the Vth curve and show new criteria for discussing SRAM array stability with Vth variability.",

keywords = "Design form manufacturability (DFM), Local Vth variability, SRAM, Static noise margin",

author = "Yasumasa Tsukamoto and Koji Nii and Susumu Imaoka and Yuji Oda and Shigeki Ohbayashi and Tomoaki Yoshizawa and Hiroshi Makino and Koichiro Ishibashi and Hirofumi Shinohara",

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AU - Tsukamoto, Yasumasa

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AU - Imaoka, Susumu

AU - Oda, Yuji

AU - Ohbayashi, Shigeki

AU - Yoshizawa, Tomoaki

AU - Makino, Hiroshi

AU - Ishibashi, Koichiro

AU - Shinohara, Hirofumi

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AB - 6T-SRAM cells in the sub-100 nm CMOS generation are now being exposed to a fatal risk that originates from large local Vth variability (σ V_Local). To achieve high-yield SRAM arrays in presence of random σV_Local component, we propose worst-case analysis that determines the boundary of the stable Vth region for the SRAM read/write DC margin (Vth curve). Applying this to our original 65 nm SPICE model, we demonstrate typical behavior of the Vth curve and show new criteria for discussing SRAM array stability with Vth variability.

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Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability

Abstract

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Keywords

ASJC Scopus subject areas

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