柳澤 政生

研究成果

年別の研究成果 1998 2004 2012 2015 2016 2017 2018 2019 2022

• 126 Conference contribution
• 107 Article
• 9 Paper
• 4 Conference article
• 3 その他
  • 2 Chapter
  • 1 Letter

年別の研究成果

年別の研究成果

検索結果

• 2022

  Dataflow Optimization through Exploring Single-Layer and Inter-Layer Data Reuse in Memory-Constrained Accelerators

  Ye, J., Yanagisawa, M. & Shi, Y., 2022 8月, In: Electronics (Switzerland). 11, 15, 2356.

  研究成果: Article › 査読

  Open Access

  • Particle accelerators 100%
  • Data storage equipment 60%
  • Neural networks 35%

• Scalable Hardware Efficient Architecture for Parallel FIR Filters with Symmetric Coefficients

  Ye, J., Yanagisawa, M. & Shi, Y., 2022 10月, In: Electronics (Switzerland). 11, 20, 3272.

  研究成果: Article › 査読

  Open Access

  • FIR filters 100%
  • Convolution 59%
  • Computer hardware 52%
  • Parallel architectures 34%
  • Signal processing 24%
  1 被引用数 (Scopus)
• 2021

  Power-Efficient Deep Convolutional Neural Network Design through Zero-Gating PEs and Partial-Sum Reuse Centric Dataflow

  Ye, L., Ye, J., Yanagisawa, M. & Shi, Y., 2021, In: IEEE Access.

  研究成果: Article › 査読

  Open Access

  • Deep neural networks 100%
  • Convolutional neural networks 93%
  • Convolution 60%
  • Chemical activation 55%
  • Dynamic random access storage 47%
  3 被引用数 (Scopus)
• 2020

  Faithfully truncated adder-based area-power efficient FIR design with predefined output accuracy

  Ye, J., Yanagisawa, M. & Shi, Y., 2020 9月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E103A, 9, p. 1063-1070 8 p.

  研究成果: Article › 査読

  • Impulse Response 100%
  • Adders 92%
  • Impulse response 86%
  • Output 63%
  • Design 52%
  1 被引用数 (Scopus)

• Scalable stochastic number duplicators for accuracy-flexible arithmetic circuit design

  Ishikawa, R., Tawada, M., Yanagisawa, M. & Togawa, N., 2020, In: IPSJ Transactions on System LSI Design Methodology. 13, p. 10-20 11 p.

  研究成果: Article › 査読

  Open Access

  • Networks (circuits) 100%
  • Flip flop circuits 52%
  • Logic circuits 51%
  1 被引用数 (Scopus)

• Transition Detector-Based Radiation-Hardened Latch for Both Single- And Multiple-Node Upsets

  Tajima, S., Yanagisawa, M. & Shi, Y., 2020 6月, In: IEEE Transactions on Circuits and Systems II: Express Briefs. 67, 6, p. 1114-1118 5 p., 8755273.

  研究成果: Article › 査読

  • Radiation 100%
  • Detectors 98%
  • Recovery 42%
  • Error detection 34%
  7 被引用数 (Scopus)

• Trojan-net classification for gate-level hardware design utilizing boundary net structures

  Hasegawa, K., Yanagisawa, M. & Togawa, N., 2020 7月 1, In: IEICE Transactions on Information and Systems. E103D, 7, p. 1618-1622 5 p.

  研究成果: Article › 査読

  Open Access

  • Hardware security 100%
  • Computer hardware 45%
  • Machine learning 28%
  • Security of data 18%
  4 被引用数 (Scopus)
• 2019

  A multiple cyclic-route generation method with route length constraint considering point-of-interests

  Nishimura, T., Ishikawa, K., Takayama, T., Yanagisawa, M. & Togawa, N., 2019 4月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E102A, 4, p. 641-653 13 p.

  研究成果: Article › 査読

  • Reference Point 100%
  • User Preferences 71%
  • Search Methods 45%

• An FPGA implementation method based on distributed-register architectures

  Fujiwara, K., Kawamura, K., Yanagisawa, M. & Togawa, N., 2019 2月, In: IPSJ Transactions on System LSI Design Methodology. 12, p. 38-41 4 p.

  研究成果: Article › 査読

  Open Access

  • Field programmable gate arrays (FPGA) 100%
  • Networks (circuits) 67%
  • High level synthesis 26%

• A robust indoor/outdoor detection method based on spatial and temporal features of sparse GPS measured positions

  Iwata, S., Ishikawa, K., Takayama, T., Yanagisawa, M. & Togawa, N., 2019, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E102A, 6, p. 860-865 6 p.

  研究成果: Article › 査読

  • Global positioning system 100%
  • Random forests 61%
  • Classifiers 41%
  • Random Forest 37%
  • Classifier 28%
  1 被引用数 (Scopus)

• Bicycle behavior recognition using 3-axis acceleration sensor and 3-axis gyro sensor equipped with smartphone

  Usami, Y., Ishikawa, K., Takayama, T., Yanagisawa, M. & Togawa, N., 2019, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E102A, 8, p. 953-965 13 p.

  研究成果: Article › 査読

  • Sensor 100%
  • Bicycles 99%
  • Smartphones 80%
  • Sensors 43%
  • Motion 17%
  2 被引用数 (Scopus)

• Logistic regression analysis of multiple interosseous hand-muscle activities using surface electromyography during finger-oriented tasks

  Yokoyama, M. & Yanagisawa, M., 2019 2月, In: Journal of Electromyography and Kinesiology. 44, p. 117-123 7 p.

  研究成果: Article › 査読

  • Electromyography 100%
  • Fingers 90%
  • Hand 74%
  • Regression Analysis 65%
  • Logistic Models 64%
  5 被引用数 (Scopus)
• 2018

  A low power soft error hardened latch with schmitt-trigger-based C-Element

  Tajima, S., Togawa, N., Yanagisawa, M. & Shi, Y., 2018 7月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 7, p. 1025-1034 10 p.

  研究成果: Article › 査読

  • Trigger 63%
  • Power Consumption 38%
  • Electric power utilization 17%
  • Double Sampling 15%
  • Design 14%
  4 被引用数 (Scopus)

• A relaxed bit-write-reducing and error-correcting code for non-volatile memories

  Kojo, T., Tawada, M., Yanagisawa, M. & Togawa, N., 2018 7月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 7, p. 1045-1052 8 p.

  研究成果: Article › 査読

  • Error-correcting Codes 100%
  • Data storage equipment 51%
  • Crosstalk 27%
  • Systematic Error 23%
  • Error Correction 22%

• A stayed location estimation method for sparse GPS positioning information based on positioning accuracy and short-time cluster removal

  Iwata, S., Nitta, T., Takayama, T., Yanagisawa, M. & Togawa, N., 2018 5月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 5, p. 831-843 13 p.

  研究成果: Article › 査読

  • Location Estimation 100%
  • Positioning 83%
  • Global positioning system 52%
  • Mobile Devices 18%
  • Battery 14%
  2 被引用数 (Scopus)

• Empirical evaluation and optimization of hardware-Trojan classification for gate-level netlists based on multi-layer neural networks

  Hasegawa, K., Yanagisawa, M. & Togawa, N., 2018 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 12, p. 2320-2326 7 p.

  研究成果: Article › 査読

  • Multilayer Neural Network 100%
  • Hardware security 78%
  • Hardware 74%
  • Multilayer neural networks 62%
  • Optimization 46%
  9 被引用数 (Scopus)

• Extension and performance/accuracy formulation for optimal GeAr-based approximate adder designs

  Hayamizu, K., Togawa, N., Yanagisawa, M. & Shi, Y., 2018 7月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 7, p. 1014-1024 11 p.

  研究成果: Article › 査読

  • Approximate Design 100%
  • Adders 72%
  • Gears 57%
  • Formulation 41%
  • Energy Consumption 40%
  1 被引用数 (Scopus)

• Hardware trojan detection and classification based on logic testing utilizing steady state learning

  Oya, M., Yanagisawa, M. & Togawa, N., 2018 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 12, p. 2308-2319 12 p.

  研究成果: Article › 査読

  • Hardware security 100%
  • Hardware 95%
  • Learning 71%
  • Logic 61%
  • Testing 55%
  2 被引用数 (Scopus)

• Scan-based side-channel attack against HMAC-SHA-256 circuits based on isolating bit-transition groups using scan signatures

  Oku, D., Yanagisawa, M. & Togawa, N., 2018 2月, In: IPSJ Transactions on System LSI Design Methodology. 11, p. 16-28 13 p.

  研究成果: Article › 査読

  • Side channel attack 100%
  • Networks (circuits) 44%
  2 被引用数 (Scopus)

• Stochastic number duplicators based on bit re-arrangement using randomized bit streams

  Ishikawa, R., Tawada, M., Yanagisawa, M. & Togawa, N., 2018 7月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 7, p. 1002-1013 12 p.

  研究成果: Article › 査読

  • Rearrangement 100%
  • Logic circuits 21%
  • Networks (circuits) 20%
  • Mean square error 17%
  • Experimental Evaluation 16%
  5 被引用数 (Scopus)
• 2017

  A bitwidth-aware high-level synthesis algorithm using operation chainings for tiled-DR architectures

  Terada, K., Yanagisawa, M. & Togawa, N., 2017 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 12, p. 2911-2924 14 p.

  研究成果: Article › 査読

  • High-level Synthesis 100%
  • High level synthesis 64%
  • Architecture 56%
  • Controller 48%
  • Controllers 27%

• A floorplan aware high-level synthesis algorithm with body biasing for delay variation compensation

  Igawa, K., Yanagisawa, M. & Togawa, N., 2017 7月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 7, p. 1439-1451 13 p.

  研究成果: Article › 査読

  • High-level Synthesis 100%
  • Leakage 66%
  • High level synthesis 64%
  • Bias voltage 63%
  • Compensation and Redress 38%

• A hardware-trojan classification method using machine learning at gate-level netlists based on Trojan features

  Hasegawa, K., Yanagisawa, M. & Togawa, N., 2017 7月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 7, p. 1427-1438 12 p.

  研究成果: Article › 査読

  • Hardware security 100%
  • Hardware 95%
  • Machine Learning 85%
  • Machine learning 57%
  • Support Vector Machine 32%
  29 被引用数 (Scopus)

• An Evaluation of Hand-Force Prediction Using Artificial Neural-Network Regression Models of Surface EMG Signals for Handwear Devices

  Yokoyama, M., Koyama, R. & Yanagisawa, M., 2017, In: Journal of Sensors. 2017, 3980906.

  研究成果: Article › 査読

  • Electromyography 100%
  • regression analysis 83%
  • evaluation 51%
  • Neural networks 49%
  • Dynamometers 46%
  12 被引用数 (Scopus)

• A safe and comprehensive route finding algorithm for pedestrians based on lighting and landmark conditions

  Bao, S., Nitta, T., Yanagisawa, M. & Togawa, N., 2017 11月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 11, p. 2439-2450 12 p.

  研究成果: Article › 査読

  • Landmarks 100%
  • Lighting 60%
  • Safety 34%
  • Count 26%
  • Algorithm Design 20%
  5 被引用数 (Scopus)

• Efficient multiplexer networks for field-data extractors and their evaluations

  Ito, K., Kawamura, K., Tamiya, Y., Yanagisawa, M. & Togawa, N., 2017 4月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 4, p. 1015-1028 14 p.

  研究成果: Article › 査読

  • Extractor 100%
  • Wire 54%
  • Evaluation 52%
  • Networks (circuits) 19%
  • Output 19%

• Trojan-net feature extraction and its application to hardware-Trojan detection for gate-level netlists using random forest

  Hasegawa, K., Yanagisawa, M. & Togawa, N., 2017 12月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 12, p. 2857-2868 12 p.

  研究成果: Article › 査読

  • Feature Extraction 100%
  • Random Forest 97%
  • Hardware security 85%
  • Hardware 81%
  • Random forests 70%
  9 被引用数 (Scopus)
• 2016

  A bit-write-reducing and error-correcting code generation method by clustering ECC codewords for non-volatile memories

  Kojo, T., Tawada, M., Yanagisawa, M. & Togawa, N., 2016 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 12, p. 2398-2411 14 p.

  研究成果: Article › 査読

  • Code Generation 100%
  • Error-correcting Codes 67%
  • Clustering 54%
  • Data storage equipment 34%
  • Crosstalk 15%
  1 被引用数 (Scopus)

• A highly-adaptable and small-sized in-field power analyzer for low-power IoT devices

  Kitayama, R., Takenaka, T., Yanagisawa, M. & Togawa, N., 2016 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 12, p. 2348-2362 15 p.

  研究成果: Article › 査読

  • Internet of things 100%
  • Power Consumption 77%
  • Power Analysis 66%
  • Energy Consumption 36%
  • Electric power utilization 35%
  1 被引用数 (Scopus)

• Bi-partitioning based multiplexer network for field-data extractors

  Ito, K., Kawamura, K., Tamiya, Y., Yanagisawa, M. & Togawa, N., 2016 7月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 7, p. 1410-1414 5 p.

  研究成果: Article › 査読

  • Extractor 100%
  • Partitioning 71%
  • Stream Processing 32%
  • Experimental Results 18%
  • Count 15%
  1 被引用数 (Scopus)

• Hardware-trojans rank: Quantitative evaluation of security threats at gate-level netlists by pattern matching

  Oya, M., Yamashita, N., Okamura, T., Tsunoo, Y., Yanagisawa, M. & Togawa, N., 2016 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 12, p. 2335-2347 13 p.

  研究成果: Article › 査読

  • Quantitative Evaluation 100%
  • Hardware security 83%
  • Pattern Matching 82%
  • Hardware 79%
  • Pattern matching 74%
  10 被引用数 (Scopus)

• Multi-scenario high-level synthesis for dynamic delay variation and its evaluation on FPGA platforms

  Igawa, K., Yanagisawa, M. & Togawa, N., 2016, In: ieice electronics express. 13, 18, 20160641.

  研究成果: Article › 査読

  • High level synthesis 100%
  • registers 70%
  • platforms 65%
  • Field programmable gate arrays (FPGA) 63%
  • synthesis 56%
• 2015

  A floorplan-driven high-level synthesis algorithm for multiplexer reduction targeting FPGA designs

  Fujiwara, K., Kawamura, K., Abe, S. Y., Yanagisawa, M. & Togawa, N., 2015 7月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 7, p. 1392-1405 14 p.

  研究成果: Article › 査読

  • High-level Synthesis 100%
  • Field Programmable Gate Array 79%
  • High level synthesis 64%
  • Field programmable gate arrays (FPGA) 41%
  • Design 31%
  2 被引用数 (Scopus)

• A hardware-trojans identifying method based on trojan net scoring at gate-level netlists

  Oya, M., Shi, Y., Yamashita, N., Okamura, T., Tsunoo, Y., Goto, S., Yanagisawa, M. & Togawa, N., 2015 12月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 12, p. 2537-2546 10 p.

  研究成果: Article › 査読

  • Hardware security 100%
  • Hardware 95%
  • Scoring 93%
  • Benchmark 35%
  • Integrated circuit design 12%
  10 被引用数 (Scopus)

• A high-level synthesis algorithm with inter-island distance based operation chainings for RDR architectures

  Terada, K., Yanagisawa, M. & Togawa, N., 2015 7月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 7, p. 1366-1375 10 p.

  研究成果: Article › 査読

  • High-level Synthesis 100%
  • High level synthesis 64%
  • Architecture 56%
  • Latency 26%
  • List Scheduling 16%
  1 被引用数 (Scopus)

• An effective suspicious timing-error prediction circuit insertion algorithm minimizing area overhead

  Yoshida, S., Shi, Y., Yanagisawa, M. & Togawa, N., 2015 7月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 7, p. 1406-1418 13 p.

  研究成果: Article › 査読

  • Timing 100%
  • Prediction Error 98%
  • Networks (circuits) 46%
  • Checkpoint 30%
  • Min-cut 12%
  3 被引用数 (Scopus)

• An energy-efficient floorplan driven high-level synthesis algorithm for multiple clock domains design

  Abe, S. Y., Shi, Y., Usami, K., Yanagisawa, M. & Togawa, N., 2015 7月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 7, p. 1376-1391 16 p.

  研究成果: Article › 査読

  • High-level Synthesis 100%
  • Energy Efficient 82%
  • High level synthesis 64%
  • Clocks 43%
  • Design 31%
  1 被引用数 (Scopus)

• Code generation limiting maximum and minimum hamming distances for non-volatile memories

  Kojo, T., Tawada, M., Yanagisawa, M. & Togawa, N., 2015 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 12, p. 2484-2493 10 p.

  研究成果: Article › 査読

  • Code Generation 100%
  • Hamming distance 72%
  • Limiting 46%
  • Data storage equipment 34%
  • Error-correcting Codes 22%
  2 被引用数 (Scopus)

• ECC-Based bit-write reduction code generation for non-volatile memory

  Tawada, M., Kimura, S., Yanagisawa, M. & Togawa, N., 2015 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 12, p. 2494-2504 11 p.

  研究成果: Article › 査読

  • Code Generation 100%
  • Data storage equipment 34%
  • Energy 21%
  • Error-correcting Codes 19%
  • Cell 12%
  2 被引用数 (Scopus)

• Scan-based side-channel attack on the camellia block cipher using scan signatures

  Jiang, H., Fujishiro, M., Kodera, H., Yanagisawa, M. & Togawa, N., 2015 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 12, p. 2547-2555 9 p.

  研究成果: Article › 査読

  • Side Channel Attacks 100%
  • Block Ciphers 77%
  • Side channel attack 74%
  • Chip 38%
  • Chain 34%
  3 被引用数 (Scopus)
• 2014

  A delay-variation-aware high-level synthesis algorithm for RDR architectures

  Hagio, Y., Yanagisawa, M. & Togawa, N., 2014, In: IPSJ Transactions on System LSI Design Methodology. 7, p. 81-90 10 p.

  研究成果: Article › 査読

  • High level synthesis 100%
  • Scheduling 53%
  • Silicon 10%
  5 被引用数 (Scopus)

• Energy-efficient high-level synthesis for HDR architecture with multi-stage clock gating

  Akasaka, H., Abe, S. Y., Yanagisawa, M. & Togawa, N., 2014, In: IPSJ Transactions on System LSI Design Methodology. 7, p. 74-80 7 p.

  研究成果: Article › 査読

  • High level synthesis 100%
  • Clocks 66%
  • Energy utilization 41%

• Scan-based attack against trivium stream cipher using scan signatures

  Fujishiro, M., Yanagisawa, M. & Togawa, N., 2014 7月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E97-A, 7, p. 1444-1451 8 p.

  研究成果: Article › 査読

  • Stream Ciphers 100%
  • Shift registers 93%
  • Side channel attack 91%
  • Attack 76%
  • Internal 61%
  6 被引用数 (Scopus)

• Scan-based side-channel attack on the LED block cipher using scan signatures

  Fujishiro, M., Yanagisawa, M. & Togawa, N., 2014 12月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E97A, 12, p. 2434-2442 9 p.

  研究成果: Article › 査読

  • Side Channel Attacks 100%
  • Block Ciphers 77%
  • Side channel attack 74%
  • Encryption 71%
  • Cryptography 50%
  4 被引用数 (Scopus)
• 2013

  A high-speed trace-driven cache configuration simulator for dual-core processor L1 caches

  Tawada, M., Yanagisawa, M. & Togawa, N., 2013 6月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E96-A, 6, p. 1283-1292 10 p.

  研究成果: Article › 査読

  • Cache 100%
  • Simulator 86%
  • High Speed 82%
  • Data structures 55%
  • Trace 54%

• A thermal-aware high-level synthesis algorithm for RDR architectures through binding and allocation

  Kawamura, K., Yanagisawa, M. & Togawa, N., 2013 1月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E96-A, 1, p. 312-321 10 p.

  研究成果: Article › 査読

  • High-level Synthesis 100%
  • High level synthesis 64%
  • Architecture 56%
  • Chip 48%
  • Energy Consumption 38%
  1 被引用数 (Scopus)

• Floorplan driven architecture and high-level synthesis algorithm for dynamic multiple supply voltages

  Abe, S. Y., Shi, Y., Usami, K., Yanagisawa, M. & Togawa, N., 2013 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E96-A, 12, p. 2597-2611 15 p.

  研究成果: Article › 査読

  • High-level Synthesis 100%
  • High level synthesis 64%
  • Voltage 57%
  • Architecture 56%
  • Floorplanning 29%
  2 被引用数 (Scopus)

• Scan-based attack against DES and Triple DES cryptosystems using scan signatures

  Kodera, H., Yanagisawa, M. & Togawa, N., 2013, In: Journal of information processing. 21, 3, p. 572-579 8 p.

  研究成果: Article › 査読

  • Cryptography 100%
  • Side channel attack 21%
  2 被引用数 (Scopus)
• 2012

  A fastweighted adder by reducing partial product for reconstruction in super-resolution

  Yoshihara, H., Yanagisawa, M. & Togawa, N., 2012, In: IPSJ Transactions on System LSI Design Methodology. 5, p. 96-105 10 p.

  研究成果: Article › 査読

  • Adders 100%
  • Optical resolving power 24%
  • Image resolution 19%
  • Time delay 15%
  • Costs 13%

• A locality-aware hybrid NoC configuration algorithm utilizing the communication volume among IP cores

  Lee, S., Yanagisawa, M. & Togawa, N., 2012 9月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E95-A, 9, p. 1538-1549 12 p.

  研究成果: Article › 査読

  • Network on chip 100%
  • Intellectual property core 63%
  • Locality 59%
  • Network-on-chip 56%
  • Communication 45%
  1 被引用数 (Scopus)