戸川 望

研究成果

年別の研究成果 1994 2012 2015 2016 2017 2018 2019 2020 2021 2022 2023

• 159 Conference contribution
• 124 Article
• 14 Paper
• 6 Conference article
• 9 その他
  • 5 Editorial
  • 2 Chapter
  • 1 Letter
  • 1 Review article

年別の研究成果

年別の研究成果

検索結果

• 2023

  An Efficient Combined Bit-Width Reducing Method for Ising Models

  Yachi, Y., Tawada, M. & Togawa, N., 2023 4月, In: IEICE Transactions on Information and Systems. E106D, 4, p. 495-508 14 p.

  研究成果: Article › 査読

  Open Access

  • Ising model 100%
  • Annealing 39%
  • Combinatorial optimization 26%
  • Ground state 23%
  • Electron energy levels 9%

• Multi-Spin-Flip Engineering in an Ising Machine

  Shirai, T. & Togawa, N., 2023 3月 1, In: IEEE Transactions on Computers. 72, 3, p. 759-771 13 p.

  研究成果: Article › 査読

  Open Access

  • Ising 100%
  • Hamiltonians 94%
  • Flip 90%
  • Engineering 64%
  • Ising model 62%

• R-HTDetector: Robust Hardware-Trojan Detection Based on Adversarial Training

  Hasegawa, K., Hidano, S., Nozawa, K., Kiyomoto, S. & Togawa, N., 2023 2月 1, In: IEEE Transactions on Computers. 72, 2, p. 333-345 13 p.

  研究成果: Article › 査読

  Open Access

  • Hardware security 100%
  • Hardware 95%
  • Training 82%
  • Machine Learning 36%
  • Machine learning 24%

• Spin-Variable Reduction Method for Handling Linear Equality Constraints in Lsing Machines

  Shirai, T. & Togawa, N., 2023, (Accepted/In press) In: IEEE Transactions on Computers. p. 1-14 14 p.

  研究成果: Article › 査読

  Open Access

  • Reduction Method 100%
  • Equality Constraints 98%
  • Combinatorial optimization 97%
  • Combinatorial Optimization Problem 96%
  • Linear Constraints 94%
• 2022

  Carrying-mode Free Indoor Positioning Using Smartphone and Smartwatch and Its Evaluations

  Wakaizumi, T. & Togawa, N., 2022, In: Journal of information processing. 30, p. 52-65 14 p.

  研究成果: Article › 査読

  Open Access

  • Smartphones 100%
  • Sensors 31%
  • Navigation systems 30%
  • Angular velocity 16%
  • Global positioning system 13%

• Hardware-Trojan Detection Based on the Structural Features of Trojan Circuits Using Random Forests

  Kurihara, T. & Togawa, N., 2022 7月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E105A, 7, p. 1049-1060 12 p.

  研究成果: Article › 査読

  • Random Forest 100%
  • Hardware security 87%
  • Hardware 83%
  • Random forests 72%
  • Networks (circuits) 37%
  1 被引用数 (Scopus)

• How to Reduce the Bit-Width of an Ising Model by Adding Auxiliary Spins

  Oku, D., Tawada, M., Tanaka, S. & Togawa, N., 2022 1月 1, In: IEEE Transactions on Computers. 71, 1, p. 223-234 12 p.

  研究成果: Article › 査読

  Open Access

  • Ising model 100%
  • Ising Model 73%
  • Annealing 28%
  • Combinatorial optimization 23%
  • Combinatorial Optimization Problem 22%
  4 被引用数 (Scopus)

• Hybrid Annealing Method Based on subQUBO Model Extraction with Multiple Solution Instances

  Atobe, Y., Tawada, M. & Togawa, N., 2022 10月 1, In: IEEE Transactions on Computers. 71, 10, p. 2606-2619 14 p.

  研究成果: Article › 査読

  Open Access

  • Annealing 100%
  • Multiple Solutions 81%
  • Optimization Model 74%
  • Ground State Solution 72%
  • Ising 56%

• Multi-Objective Trip Planning Based on Ant Colony Optimization Utilizing Trip Records

  Saeki, E., Bao, S., Takayama, T. & Togawa, N., 2022, In: IEEE Access. 10, p. 127825-127844 20 p.

  研究成果: Article › 査読

  Open Access

  • Pheromone 100%
  • Ant colony optimization 87%
  • Planning 50%
  • Tourism 31%
  • Information technology 23%

• Towards optimization of photonic-crystal surface-emitting lasers via quantum annealing

  Inoue, T., Seki, Y., Tanaka, S., Togawa, N., Ishizaki, K. & Noda, S., 2022 11月 21, In: Optics Express. 30, 24, p. 43503-43512 10 p.

  研究成果: Article › 査読

  Open Access

  • Optics and Photonics 100%
  • crystal surfaces 68%
  • surface emitting lasers 67%
  • Lasers 52%
  • photonics 44%
• 2021

  Analysis and Acceleration of the Quadratic Knapsack Problem on an Ising Machine

  Parizy, M. & Togawa, N., 2021 11月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E104A, 11, p. 1526-1535 10 p.

  研究成果: Article › 査読

  Open Access

  • Ground state 100%
  • Ising 83%
  • Knapsack Problem 78%
  • Cost functions 61%
  • Spin Models 30%

• An Anomalous Behavior Detection Method Utilizing Extracted Application-Specific Power Behaviors

  Takasaki, K., Kida, R. & Togawa, N., 2021 11月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E104A, 11, p. 1555-1565 11 p.

  研究成果: Article › 査読

  • Anomalous 100%
  • Application programs 76%
  • Internet of Things 68%
  • Internet of things 56%
  • Waveform 45%

• An ising machine-based solver for visiting-route recommendation problems in amusement parks

  MUKASA, Y., WAKAIZUMI, T., TANAKA, S. & TOGAWA, N., 2021, In: IEICE Transactions on Information and Systems. E104D, 10, p. 1592-1600 9 p.

  研究成果: Article › 査読

  Open Access

  • Ising model 100%
  • Combinatorial optimization 69%
  • Simulated annealing 63%

• A route recommendation method considering individual user’s preferences by monte-carlo tree search and its evaluations

  Ishizaki, Y., Koyama, Y., Takayama, T. & Togawa, N., 2021, In: Journal of information processing. 29, p. 81-92 12 p.

  研究成果: Article › 査読

  Open Access

  • Smartphones 100%
  • Support vector machines 86%
  2 被引用数 (Scopus)

• A three-stage annealing method solving slot-placement problems using an ising machine

  Fukada, K., Parizy, M., Tomita, Y. & Togawa, N., 2021, In: IEEE Access. 9, p. 134413-134426 14 p.

  研究成果: Article › 査読

  Open Access

  • Annealing 100%
  • Combinatorial optimization 88%
  • Electric wiring 43%
  • Length 24%
  • Spin State 22%
  2 被引用数 (Scopus)

• A Two-Stage Hardware Trojan Detection Method Considering the Trojan Probability of Neighbor Nets

  Hasegawa, K., Inoue, T. & Togawa, N., 2021 11月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E104.A, 11, p. 1516-1525 10 p.

  研究成果: Article › 査読

  • Hardware security 100%
  • Hardware 95%
  • Computer hardware 34%
  • Networks (circuits) 21%
  • Internet of Things 20%

• Experimental evaluations of parallel tempering on an ising machine

  Mukasa, Y., Tanaka, S. & Togawa, N., 2021, In: IPSJ Transactions on System LSI Design Methodology. 14, p. 27-29 3 p.

  研究成果: Article › 査読

  Open Access

  • Tempering 100%
  • Combinatorial optimization 97%

• Generating adversarial examples for hardware-trojan detection at gate-level netlists

  Nozawa, K., Hasegawa, K., Hidano, S., Kiyomoto, S., Hashimoto, K. & Togawa, N., 2021, In: Journal of information processing. 29, p. 236-246 11 p.

  研究成果: Article › 査読

  Open Access

  • Hardware security 100%
  • Networks (circuits) 25%
  • Machine learning 22%
  • Integrated circuit design 19%
  • Integrated circuits 14%
  4 被引用数 (Scopus)

• Mapping induced subgraph isomorphism problems to ising models and its evaluations by an ising machine

  Yoshimura, N., Tawada, M., Tanaka, S., Arai, J., Yagi, S., Uchiyama, H. & Togawa, N., 2021 4月, In: IEICE Transactions on Information and Systems. E104.D, 4, p. 481-489 9 p.

  研究成果: Article › 査読

  Open Access

  • Ising model 100%
  • Combinatorial optimization 34%
  • Chemical bonds 23%
  • Graph structures 19%
  • Simulated annealing 15%
  1 被引用数 (Scopus)

• Performance Comparison of Typical Binary-Integer Encodings in an Ising Machine

  Tamura, K., Shirai, T., Katsura, H., Tanaka, S. & Togawa, N., 2021, In: IEEE Access. 9, p. 81032-81039 8 p., 9435359.

  研究成果: Article › 査読

  Open Access

  • Ising Model 100%
  • Combinatorial optimization 69%
  • Ising model 66%
  • Ground state 31%
  • Ground State 24%
  16 被引用数 (Scopus)

• Solving constrained slot placement problems using an ising machine and its evaluations

  Kanamaru, S., Kawamura, K., Tanaka, S., Tomita, Y. & Togawa, N., 2021 2月 1, In: IEICE Transactions on Information and Systems. E104D, 2, p. 226-236 11 p.

  研究成果: Article › 査読

  Open Access

  • Ising model 100%
  • Simulated annealing 95%
  • Combinatorial optimization 69%
  • Digital circuits 35%
  • Planning 20%
  1 被引用数 (Scopus)
• 2020

  A capacitance measurement device for running hardware devices and its evaluations

  Nishizawa, M., Hasegawa, K. & Togawa, N., 2020 9月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E103A, 9, p. 1018-1027 10 p.

  研究成果: Article › 査読

  • Capacitance measurement 100%
  • Capacitance 92%
  • Hardware 84%
  • Evaluation 50%
  • Computer hardware 40%
  1 被引用数 (Scopus)

• Guiding Principle for Minor-Embedding in Simulated-Annealing-Based Ising Machines

  Shirai, T., Tanaka, S. & Togawa, N., 2020, In: IEEE Access. 8, p. 210490-210502 13 p., 9268172.

  研究成果: Article › 査読

  Open Access

  • Ising Model 100%
  • Ising model 99%
  • Simulated annealing 63%
  • Combinatorial optimization 51%
  • Statistical mechanics 46%
  4 被引用数 (Scopus)

• Scalable stochastic number duplicators for accuracy-flexible arithmetic circuit design

  Ishikawa, R., Tawada, M., Yanagisawa, M. & Togawa, N., 2020, In: IPSJ Transactions on System LSI Design Methodology. 13, p. 10-20 11 p.

  研究成果: Article › 査読

  Open Access

  • Networks (circuits) 100%
  • Flip flop circuits 52%
  • Logic circuits 51%
  1 被引用数 (Scopus)

• Trojan-net classification for gate-level hardware design utilizing boundary net structures

  Hasegawa, K., Yanagisawa, M. & Togawa, N., 2020 7月 1, In: IEICE Transactions on Information and Systems. E103D, 7, p. 1618-1622 5 p.

  研究成果: Article › 査読

  Open Access

  • Hardware security 100%
  • Computer hardware 45%
  • Machine learning 28%
  • Security of data 18%
  4 被引用数 (Scopus)
• 2019

  A fully-connected ising model embedding method and its evaluation for CMOS annealing machines

  Oku, D., Terada, K., Hayashi, M., Yamaoka, M., Tanaka, S. & Togawa, N., 2019, In: IEICE Transactions on Information and Systems. E102D, 9, p. 1696-1706 11 p.

  研究成果: Article › 査読

  Open Access

  • Ising model 100%
  • Annealing 62%
  • Combinatorial optimization 46%
  • Ground state 15%
  • Chain length 14%
  11 被引用数 (Scopus)

• A multiple cyclic-route generation method with route length constraint considering point-of-interests

  Nishimura, T., Ishikawa, K., Takayama, T., Yanagisawa, M. & Togawa, N., 2019 4月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E102A, 4, p. 641-653 13 p.

  研究成果: Article › 査読

  • Reference Point 100%
  • User Preferences 71%
  • Search Methods 45%

• An FPGA implementation method based on distributed-register architectures

  Fujiwara, K., Kawamura, K., Yanagisawa, M. & Togawa, N., 2019 2月, In: IPSJ Transactions on System LSI Design Methodology. 12, p. 38-41 4 p.

  研究成果: Article › 査読

  Open Access

  • Field programmable gate arrays (FPGA) 100%
  • Networks (circuits) 67%
  • High level synthesis 26%

• A robust indoor/outdoor detection method based on spatial and temporal features of sparse GPS measured positions

  Iwata, S., Ishikawa, K., Takayama, T., Yanagisawa, M. & Togawa, N., 2019, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E102A, 6, p. 860-865 6 p.

  研究成果: Article › 査読

  • Global positioning system 100%
  • Random forests 61%
  • Classifiers 41%
  • Random Forest 37%
  • Classifier 28%
  1 被引用数 (Scopus)

• Bicycle behavior recognition using 3-axis acceleration sensor and 3-axis gyro sensor equipped with smartphone

  Usami, Y., Ishikawa, K., Takayama, T., Yanagisawa, M. & Togawa, N., 2019, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E102A, 8, p. 953-965 13 p.

  研究成果: Article › 査読

  • Sensor 100%
  • Bicycles 99%
  • Smartphones 80%
  • Sensors 43%
  • Motion 17%
  2 被引用数 (Scopus)
• 2018

  A low power soft error hardened latch with schmitt-trigger-based C-Element

  Tajima, S., Togawa, N., Yanagisawa, M. & Shi, Y., 2018 7月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 7, p. 1025-1034 10 p.

  研究成果: Article › 査読

  • Trigger 63%
  • Power Consumption 38%
  • Electric power utilization 17%
  • Double Sampling 15%
  • Design 14%
  4 被引用数 (Scopus)

• A relaxed bit-write-reducing and error-correcting code for non-volatile memories

  Kojo, T., Tawada, M., Yanagisawa, M. & Togawa, N., 2018 7月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 7, p. 1045-1052 8 p.

  研究成果: Article › 査読

  • Error-correcting Codes 100%
  • Data storage equipment 51%
  • Crosstalk 27%
  • Systematic Error 23%
  • Error Correction 22%

• A stayed location estimation method for sparse GPS positioning information based on positioning accuracy and short-time cluster removal

  Iwata, S., Nitta, T., Takayama, T., Yanagisawa, M. & Togawa, N., 2018 5月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 5, p. 831-843 13 p.

  研究成果: Article › 査読

  • Location Estimation 100%
  • Positioning 83%
  • Global positioning system 52%
  • Mobile Devices 18%
  • Battery 14%
  2 被引用数 (Scopus)

• Empirical evaluation and optimization of hardware-Trojan classification for gate-level netlists based on multi-layer neural networks

  Hasegawa, K., Yanagisawa, M. & Togawa, N., 2018 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 12, p. 2320-2326 7 p.

  研究成果: Article › 査読

  • Multilayer Neural Network 100%
  • Hardware security 78%
  • Hardware 74%
  • Multilayer neural networks 62%
  • Optimization 46%
  9 被引用数 (Scopus)

• Extension and performance/accuracy formulation for optimal GeAr-based approximate adder designs

  Hayamizu, K., Togawa, N., Yanagisawa, M. & Shi, Y., 2018 7月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 7, p. 1014-1024 11 p.

  研究成果: Article › 査読

  • Approximate Design 100%
  • Adders 72%
  • Gears 57%
  • Formulation 41%
  • Energy Consumption 40%
  1 被引用数 (Scopus)

• Hardware trojan detection and classification based on logic testing utilizing steady state learning

  Oya, M., Yanagisawa, M. & Togawa, N., 2018 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 12, p. 2308-2319 12 p.

  研究成果: Article › 査読

  • Hardware security 100%
  • Hardware 95%
  • Learning 71%
  • Logic 61%
  • Testing 55%
  2 被引用数 (Scopus)

• Scan-based side-channel attack against HMAC-SHA-256 circuits based on isolating bit-transition groups using scan signatures

  Oku, D., Yanagisawa, M. & Togawa, N., 2018 2月, In: IPSJ Transactions on System LSI Design Methodology. 11, p. 16-28 13 p.

  研究成果: Article › 査読

  • Side channel attack 100%
  • Networks (circuits) 44%
  2 被引用数 (Scopus)

• Stochastic number duplicators based on bit re-arrangement using randomized bit streams

  Ishikawa, R., Tawada, M., Yanagisawa, M. & Togawa, N., 2018 7月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 7, p. 1002-1013 12 p.

  研究成果: Article › 査読

  • Rearrangement 100%
  • Logic circuits 21%
  • Networks (circuits) 20%
  • Mean square error 17%
  • Experimental Evaluation 16%
  5 被引用数 (Scopus)
• 2017

  A bitwidth-aware high-level synthesis algorithm using operation chainings for tiled-DR architectures

  Terada, K., Yanagisawa, M. & Togawa, N., 2017 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 12, p. 2911-2924 14 p.

  研究成果: Article › 査読

  • High-level Synthesis 100%
  • High level synthesis 64%
  • Architecture 56%
  • Controller 48%
  • Controllers 27%

• A floorplan aware high-level synthesis algorithm with body biasing for delay variation compensation

  Igawa, K., Yanagisawa, M. & Togawa, N., 2017 7月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 7, p. 1439-1451 13 p.

  研究成果: Article › 査読

  • High-level Synthesis 100%
  • Leakage 66%
  • High level synthesis 64%
  • Bias voltage 63%
  • Compensation and Redress 38%

• A hardware-trojan classification method using machine learning at gate-level netlists based on Trojan features

  Hasegawa, K., Yanagisawa, M. & Togawa, N., 2017 7月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 7, p. 1427-1438 12 p.

  研究成果: Article › 査読

  • Hardware security 100%
  • Hardware 95%
  • Machine Learning 85%
  • Machine learning 57%
  • Support Vector Machine 32%
  27 被引用数 (Scopus)

• A safe and comprehensive route finding algorithm for pedestrians based on lighting and landmark conditions

  Bao, S., Nitta, T., Yanagisawa, M. & Togawa, N., 2017 11月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 11, p. 2439-2450 12 p.

  研究成果: Article › 査読

  • Landmarks 100%
  • Lighting 60%
  • Safety 34%
  • Count 26%
  • Algorithm Design 20%
  5 被引用数 (Scopus)

• Efficient multiplexer networks for field-data extractors and their evaluations

  Ito, K., Kawamura, K., Tamiya, Y., Yanagisawa, M. & Togawa, N., 2017 4月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 4, p. 1015-1028 14 p.

  研究成果: Article › 査読

  • Extractor 100%
  • Wire 54%
  • Evaluation 52%
  • Networks (circuits) 19%
  • Output 19%

• Trojan-net feature extraction and its application to hardware-Trojan detection for gate-level netlists using random forest

  Hasegawa, K., Yanagisawa, M. & Togawa, N., 2017 12月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 12, p. 2857-2868 12 p.

  研究成果: Article › 査読

  • Feature Extraction 100%
  • Random Forest 97%
  • Hardware security 85%
  • Hardware 81%
  • Random forests 70%
  9 被引用数 (Scopus)
• 2016

  A bit-write-reducing and error-correcting code generation method by clustering ECC codewords for non-volatile memories

  Kojo, T., Tawada, M., Yanagisawa, M. & Togawa, N., 2016 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 12, p. 2398-2411 14 p.

  研究成果: Article › 査読

  • Code Generation 100%
  • Error-correcting Codes 67%
  • Clustering 54%
  • Data storage equipment 34%
  • Crosstalk 15%
  1 被引用数 (Scopus)

• A highly-adaptable and small-sized in-field power analyzer for low-power IoT devices

  Kitayama, R., Takenaka, T., Yanagisawa, M. & Togawa, N., 2016 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 12, p. 2348-2362 15 p.

  研究成果: Article › 査読

  • Internet of things 100%
  • Power Consumption 77%
  • Power Analysis 66%
  • Energy Consumption 36%
  • Electric power utilization 35%
  1 被引用数 (Scopus)

• Bi-partitioning based multiplexer network for field-data extractors

  Ito, K., Kawamura, K., Tamiya, Y., Yanagisawa, M. & Togawa, N., 2016 7月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 7, p. 1410-1414 5 p.

  研究成果: Article › 査読

  • Extractor 100%
  • Partitioning 71%
  • Stream Processing 32%
  • Experimental Results 18%
  • Count 15%
  1 被引用数 (Scopus)

• Hardware-trojans rank: Quantitative evaluation of security threats at gate-level netlists by pattern matching

  Oya, M., Yamashita, N., Okamura, T., Tsunoo, Y., Yanagisawa, M. & Togawa, N., 2016 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 12, p. 2335-2347 13 p.

  研究成果: Article › 査読

  • Quantitative Evaluation 100%
  • Hardware security 83%
  • Pattern Matching 82%
  • Hardware 79%
  • Pattern matching 74%
  10 被引用数 (Scopus)

• Multi-scenario high-level synthesis for dynamic delay variation and its evaluation on FPGA platforms

  Igawa, K., Yanagisawa, M. & Togawa, N., 2016, In: ieice electronics express. 13, 18, 20160641.

  研究成果: Article › 査読

  • High level synthesis 100%
  • registers 70%
  • platforms 65%
  • Field programmable gate arrays (FPGA) 63%
  • synthesis 56%
• 2015

  A floorplan-driven high-level synthesis algorithm for multiplexer reduction targeting FPGA designs

  Fujiwara, K., Kawamura, K., Abe, S. Y., Yanagisawa, M. & Togawa, N., 2015 7月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 7, p. 1392-1405 14 p.

  研究成果: Article › 査読

  • High-level Synthesis 100%
  • Field Programmable Gate Array 79%
  • High level synthesis 64%
  • Field programmable gate arrays (FPGA) 41%
  • Design 31%
  2 被引用数 (Scopus)