メインナビゲーションにスキップ
検索にスキップ
メインコンテンツにスキップ
早稲田大学 ホーム
English
日本語
ホーム
プロファイル
研究部門
研究成果
専門知識、名前、または所属機関で検索
Scopus著者プロファイル
史 又華
教授
Professor 教授
,
基幹理工学部
ウェブサイト
https://w-rdb.waseda.jp/html/100000830_ja.html
h-index
533
被引用数
12
h 指数
Pureの文献数とScopusの被引用数に基づいて算出されます
2001
2025
年別の研究成果
概要
フィンガープリント
ネットワーク
研究成果
(79)
類似のプロファイル
(5)
フィンガープリント
Youhua Shiが活動している研究トピックを掘り下げます。このトピックラベルは、この研究者の研究成果に基づきます。これらがまとまってユニークなフィンガープリントを構成します。
並べ替え順
重み付け
アルファベット順
Computer Science
Advanced Encryption Standard
24%
Architecture Register
34%
Checkpoint Selection
12%
Classification Method
12%
Compression Technique
43%
Conventional Algorithm
14%
Critical Path
18%
Data Compression
32%
Deep Convolutional Neural Networks
12%
Delay Variation
28%
Density Functional Theory
14%
Design Challenge
14%
Design Phase
18%
Driven Architecture
15%
Effective Solution
12%
Energy Efficient
36%
Energy Saving
13%
Error Detection
16%
Experimental Result
100%
Fault Coverage
15%
Fault Diagnosis
24%
Finite Impulse Response Filter
18%
Floorplanning
28%
Functional Unit
14%
Handling Technique
12%
Hashing Algorithm
12%
High Level Synthesis
85%
Insertion Algorithm
12%
linear-feedback shift register
24%
Low Power Consumption
22%
Multiple Scan Chain
24%
Object Detection
14%
Parallel Architectures
18%
Path Selection Algorithm
24%
Power Consumption
23%
Power Efficient
36%
Prediction Error
24%
Process Variation
12%
Processing Element
24%
Scan Chain
73%
Side Channel Attack
48%
Soft Error
24%
Supply Voltage
30%
Symmetric Key Cipher
12%
Synthesis Algorithm
72%
Synthesis Technique
12%
Test Application Time
30%
Test Compression
36%
Test Data Volume
69%
Test Generation
33%
Engineering
Adders
48%
Area Overhead
27%
Area Reduction
12%
Built-in Self Test
36%
Coding Efficiency
12%
Compactor
30%
Compression Method
18%
Compression Technique
39%
Compression Test
18%
Computation Complexity
14%
Convolutional Neural Network
24%
Cost Reduction
18%
Critical Path
21%
Data Rate
12%
Data Volume
46%
Digital Converter
12%
Digital Signal Processing
12%
Directional
12%
Electric Power Utilization
61%
Energy Engineering
20%
Error Detection
16%
Experimental Result
43%
Finite Impulse Response
24%
FIR Filter
29%
Hardware Accelerator
12%
Input Register
12%
Interface Circuit
12%
Internals
24%
Joints (Structural Components)
18%
Mixed Sequence
12%
Mode Selection
12%
Nodes
18%
Parallelism
12%
Pattern Generator
12%
Processing Element
36%
Product Design
12%
Reconfiguration
24%
Reusability
12%
Run Length
24%
Scan Path
12%
Selection Algorithm
12%
Self-Powered
14%
Shift Register
18%
Side Channel Attack
12%
Soft Error
16%
Test Data
70%
Test Technique
18%
Test Time
12%
Triboelectric Nanogenerators
36%
Voltage Scaling
12%
Keyphrases
32-bit Processor
12%
Adaptive Voltage
13%
Adder Design
12%
Advanced Encryption Standard
12%
Approximate Adder
12%
Body Biasing
12%
Checkpoint Selection
12%
Clock Glitch
12%
Compression Techniques
24%
Cryptographic Hardware
18%
Delay Variation
24%
Differential Fault Analysis
12%
Energy Efficient
12%
Fan-out
12%
Fault Coverage
15%
Floorplanning
32%
Gate-level Netlist
24%
Hardware Trojan
24%
High-level Synthesis
36%
Huddle
20%
Hybrid Dictionary
12%
In-situ Error Detection
12%
Instruction Set Extensions
12%
Interconnect Delay
18%
Low Power BIST
24%
Mixed Encoding
12%
Montgomery Modular multiplication
24%
Multi-scan
12%
Parallel FIR Filter
12%
Processing Element Design
20%
Radix
24%
Response Design
12%
Scan Architecture
12%
Scan Chain
15%
Scan Test
13%
Secure Scan Design
16%
SHA-3
12%
Subchain
17%
Symmetric Cipher
12%
Synthesis Algorithm
24%
Test Cost Reduction
15%
Test Data Compression
24%
Test Data Volume
18%
Test Pattern
12%
Test Quality
16%
Timing Error Prediction
12%
Transition Delay Fault
12%
Triboelectric Nanogenerator
12%
Unified Dual
24%
Zero-gating
24%
