TY - GEN
T1 - 10μW/cm2-class high power density planar Si-nanowire thermoelectric energy harvester compatible with CMOS-VLSI technology
AU - Tomita, M.
AU - Oba, S.
AU - Himeda, Y.
AU - Yamato, R.
AU - Shima, K.
AU - Kumada, T.
AU - Xu, M.
AU - Takezawa, H.
AU - Mesaki, K.
AU - Tsuda, K.
AU - Hashimoto, S.
AU - Zhan, T.
AU - Zhang, H.
AU - Kamakura, Y.
AU - Suzuki, Y.
AU - Inokawa, H.
AU - Ikeda, H.
AU - Matsukawa, T.
AU - Matsuki, T.
AU - Watanabe, T.
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2018/10/25
Y1 - 2018/10/25
N2 - A best benchmark of Si-nanowire (NW) thermoelectric (TE) power generator has been achieved by our proposed planar device architecture compatible with CMOS process technology. The TE power density corresponds to 12 μW/cm2, which is recorded at an externally applied temperature difference of only 5 K. The demonstration opens up a pathway to cost effective autonomous internet of things (IoT) application utilizing environmental and body heats.
AB - A best benchmark of Si-nanowire (NW) thermoelectric (TE) power generator has been achieved by our proposed planar device architecture compatible with CMOS process technology. The TE power density corresponds to 12 μW/cm2, which is recorded at an externally applied temperature difference of only 5 K. The demonstration opens up a pathway to cost effective autonomous internet of things (IoT) application utilizing environmental and body heats.
UR - http://www.scopus.com/inward/record.url?scp=85055366686&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85055366686&partnerID=8YFLogxK
U2 - 10.1109/VLSIT.2018.8510659
DO - 10.1109/VLSIT.2018.8510659
M3 - Conference contribution
AN - SCOPUS:85055366686
T3 - Digest of Technical Papers - Symposium on VLSI Technology
SP - 93
EP - 94
BT - 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 38th IEEE Symposium on VLSI Technology, VLSI Technology 2018
Y2 - 18 June 2018 through 22 June 2018
ER -