TY - GEN
T1 - 1.047GHz, 1.2V, 90nm CMOS, 2-way VLIW DSP core using saturation anticipator circuit
AU - Suzuki, H.
AU - Takata, H.
AU - Shinohara, H.
AU - Teraoka, E.
AU - Matsuo, M.
AU - Yoshida, T.
AU - Sato, H.
AU - Honda, N.
AU - Masui, N.
AU - Shimizu, T.
N1 - Copyright:
Copyright 2008 Elsevier B.V., All rights reserved.
PY - 2006
Y1 - 2006
N2 - 1.047GHz synthesizable 2-way VLIW General Purpose DSP core has been developed by 1.2V 90nm CMOS technology. The key technology is to detect saturation from adder's inputs in an ALU and parallelize the saturation check with the adder operation. The proposed saturation anticipator circuit and the logic structure optimization improve DSP's clock frequency by 20.8%. The test chip also runs 0.10uW/MHz at 0.8V low power operation mode.
AB - 1.047GHz synthesizable 2-way VLIW General Purpose DSP core has been developed by 1.2V 90nm CMOS technology. The key technology is to detect saturation from adder's inputs in an ALU and parallelize the saturation check with the adder operation. The proposed saturation anticipator circuit and the logic structure optimization improve DSP's clock frequency by 20.8%. The test chip also runs 0.10uW/MHz at 0.8V low power operation mode.
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M3 - Conference contribution
AN - SCOPUS:39749184810
SN - 1424400066
SN - 9781424400065
T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers
SP - 152
EP - 153
BT - 2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
T2 - 2006 Symposium on VLSI Circuits, VLSIC
Y2 - 15 June 2006 through 17 June 2006
ER -