135 GHz 98mW 10 Gbps CMOS Amplitude Shift Keying Transmitter and Receiver Chipset

Mizuki Motoyoshi, Naoko Ono, Kosuke Katayama, Kyoya Takano, Minoru Fujishima

研究成果: Article査読

3 被引用数 (Scopus)

抄録

An amplitude shift keying transmitter and receiver chipset with low power consumption using 40 nm CMOS technology for wireless communication systems is described, in which a maximum data rate of 10 Gbps and power consumption of 98.4mW are obtained with a carrier frequency of 135 GHz. A simple circuit and a modulation method to reduce power consumption are selected for the chipsets. To realize multigigabit wireless communication, the receiver is designed considering the group delay optimization. In the receiver design, the low-noise amplifier and detector are designed considering the total optimization of the gain and group delay in the millimeter-wave modulated signal region

本文言語English
ページ(範囲)86-93
ページ数8
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E97-A
1
DOI
出版ステータスPublished - 2014 1月
外部発表はい

ASJC Scopus subject areas

  • 信号処理
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学
  • 応用数学

フィンガープリント

「135 GHz 98mW 10 Gbps CMOS Amplitude Shift Keying Transmitter and Receiver Chipset」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル