TY - GEN
T1 - 14.4mW 10Gbps CMOS limiting amplifier with local DC offset cancellers
AU - Takano, Kyoya
AU - Fujimoto, Ryuichi
AU - Motoyoshi, Mizuki
AU - Katayama, Kosuke
AU - Fujishima, Minoru
PY - 2013/5/1
Y1 - 2013/5/1
N2 - A low-power limiting amplifier (LA) with DC offset cancellers (DCOCs) using local feedback loops is presented for D-band wireless transceivers. The number of cascaded stages of amplifiers is set to minimize the gain-bandwidth product (GBW) of each amplifier that has the required bandwidth to realize low power dissipation. The capacitance used in each DCOC is reduced by the local feedback loops. In addition, the area used by the capacitors in each DCOC is reduced by arranging metal-oxide-metal (MOM) capacitors on MOS capacitors. Moreover, a push-pull-type topology using only NMOSs is used as an output buffer to reduce the power dissipation. Furthermore, an inductive peaking technique is used for amplifiers to realize a large bandwidth. The proposed LA has been fabricated by a 40nm CMOS process. It has a differential voltage gain of 45dB, a bandwidth of approximately 6.5GHz, a power dissipation of 14.4mW, and a circuit area of 0.15mm2. It can operate with a data rate of 10Gbps.
AB - A low-power limiting amplifier (LA) with DC offset cancellers (DCOCs) using local feedback loops is presented for D-band wireless transceivers. The number of cascaded stages of amplifiers is set to minimize the gain-bandwidth product (GBW) of each amplifier that has the required bandwidth to realize low power dissipation. The capacitance used in each DCOC is reduced by the local feedback loops. In addition, the area used by the capacitors in each DCOC is reduced by arranging metal-oxide-metal (MOM) capacitors on MOS capacitors. Moreover, a push-pull-type topology using only NMOSs is used as an output buffer to reduce the power dissipation. Furthermore, an inductive peaking technique is used for amplifiers to realize a large bandwidth. The proposed LA has been fabricated by a 40nm CMOS process. It has a differential voltage gain of 45dB, a bandwidth of approximately 6.5GHz, a power dissipation of 14.4mW, and a circuit area of 0.15mm2. It can operate with a data rate of 10Gbps.
KW - CMOS
KW - DC offset canceller
KW - amplifier array
KW - limiting amplifiers
UR - http://www.scopus.com/inward/record.url?scp=84876756289&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84876756289&partnerID=8YFLogxK
U2 - 10.1109/RWS.2013.6486699
DO - 10.1109/RWS.2013.6486699
M3 - Conference contribution
AN - SCOPUS:84876756289
SN - 9781467329309
T3 - IEEE Radio and Wireless Symposium, RWS
SP - 235
EP - 237
BT - RSW 2013 - 2013 IEEE Radio and Wireless Symposium - RWW 2013
T2 - 2013 IEEE Radio and Wireless Symposium, RSW 2013 - 2013 7th IEEE Radio and Wireless Week, RWW 2013
Y2 - 20 January 2013 through 23 January 2013
ER -