TY - JOUR
T1 - 16Mb DRAM/SOI Technologies for Sub-1V Operation
AU - Oashi, T.
AU - Eimori, T.
AU - Morishita, F.
AU - Iwamatsu, T.
AU - Yamaguchi, Y.
AU - Okuda, F.
AU - Shimomura, K.
AU - Shimano, H.
AU - Sakashita, N.
AU - Arimoto, K.
AU - Inoue, Y.
AU - Komori, S.
AU - Inuishi, M.
AU - Nishimura, T.
AU - Miyoshi, H.
N1 - Publisher Copyright:
© 1996 IEEE
PY - 1996
Y1 - 1996
N2 - Extra low voltage D M S O 1technologies were developed using (1) modified MESA isolation without parasitic MOS operation, (2) dual gate CMOS for low Vth control, (3) optimized layout using both body-tied and floating body MOSFET’s, and (4)reduced Cb/Cs ratio. Completely redesigned low voltage scheme 16MDRAM/SOIwas successfullyrealized and functional operation was obtained at very low supply voltage below 1v.
AB - Extra low voltage D M S O 1technologies were developed using (1) modified MESA isolation without parasitic MOS operation, (2) dual gate CMOS for low Vth control, (3) optimized layout using both body-tied and floating body MOSFET’s, and (4)reduced Cb/Cs ratio. Completely redesigned low voltage scheme 16MDRAM/SOIwas successfullyrealized and functional operation was obtained at very low supply voltage below 1v.
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U2 - 10.1109/IEDM.1996.554057
DO - 10.1109/IEDM.1996.554057
M3 - Conference article
AN - SCOPUS:0030422230
SN - 0163-1918
SP - 609
EP - 612
JO - Technical Digest - International Electron Devices Meeting, IEDM
JF - Technical Digest - International Electron Devices Meeting, IEDM
T2 - Proceedings of the 1996 IEEE International Electron Devices Meeting
Y2 - 8 December 1996 through 11 December 1996
ER -