TY - JOUR
T1 - 18-BIT FLOATING-POINT SIGNAL PROCESSOR VLSI WITH AN ON-CHIP 512W DUAL-PORT RAM.
AU - Yamauchi, Hironori
AU - Kaneko, Takao
AU - Kobayashi, Tsutomu
AU - Iwata, Atsushi
AU - Ono, Sadayasu
PY - 1985/12/1
Y1 - 1985/12/1
N2 - A brand-new floating-point digital speech signal processor (DSSP) VLSI, intended for a wide range of applications in speech processing, has been developed. For speech applications, a wide-dynamic-range vector operation that includes FFT and complex arithmetic is necessary in executing a highly-complicated coding algorithm that treats a large amount of windowed data collectively. It is shown at length how the floating-point data format and hardware architecture meet this requirement. The DSSP, which is fabricated using 2. 5 mu m CMOS technology, completes almost all the floating-point operations within a 150-ns machine-cycle.
AB - A brand-new floating-point digital speech signal processor (DSSP) VLSI, intended for a wide range of applications in speech processing, has been developed. For speech applications, a wide-dynamic-range vector operation that includes FFT and complex arithmetic is necessary in executing a highly-complicated coding algorithm that treats a large amount of windowed data collectively. It is shown at length how the floating-point data format and hardware architecture meet this requirement. The DSSP, which is fabricated using 2. 5 mu m CMOS technology, completes almost all the floating-point operations within a 150-ns machine-cycle.
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M3 - Conference article
AN - SCOPUS:0022245510
SN - 0736-7791
SP - 204
EP - 207
JO - Proceedings - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing
JF - Proceedings - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing
ER -