1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times

T. Ohsawa; H. Koike; S. Miura; H. Honjo; K. Tokutome; S. Ikeda; T. Hanyu; H. Ohno; T. Endoh

doi:10.1109/VLSIC.2012.6243782

1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times

T. Ohsawa^*, H. Koike, S. Miura, H. Honjo, K. Tokutome, S. Ikeda, T. Hanyu, H. Ohno, T. Endoh

^*この研究の対応する著者

研究成果: Conference contribution

59 被引用数 (Scopus)

抄録

A 1Mb nonvolatile STT-RAM using the 4T-2MTJ cell is designed and fabricated using 90nm CMOS and MTJ processes. 32 cells along a word line (WL) are simultaneously power-gated with quick wake-up/power-off times of 1.0ns/200ps, respectively, to reduce operation power and to eliminate standby power of the chip. The cell is experimentally shown to retain data with static noise margin (SNM) 0.32V under V _dd=1V. The 1Mb chip with 2.19μm ² cell is successfully operated with array access time of 8ns and read power of 10.7mW under 10ns cycle. The macro size of 1Mb STT-RAM is predicted to become smaller than the 1Mb 6T-SRAM in 45nm and beyond.

本文言語	English
ホスト出版物のタイトル	2012 Symposium on VLSI Circuits, VLSIC 2012
ページ	46-47
ページ数	2
DOI	https://doi.org/10.1109/VLSIC.2012.6243782
出版ステータス	Published - 2012 9月 28
外部発表	はい
イベント	2012 Symposium on VLSI Circuits, VLSIC 2012 - Honolulu, HI, United States 継続期間: 2012 6月 13 → 2012 6月 15

出版物シリーズ

名前	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other	2012 Symposium on VLSI Circuits, VLSIC 2012
国/地域	United States
City	Honolulu, HI
Period	12/6/13 → 12/6/15

ASJC Scopus subject areas

電子材料、光学材料、および磁性材料
電子工学および電気工学

文献へのアクセス

10.1109/VLSIC.2012.6243782

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引用スタイル

Ohsawa, T., Koike, H., Miura, S., Honjo, H., Tokutome, K., Ikeda, S., Hanyu, T., Ohno, H., & Endoh, T. (2012). 1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times. In 2012 Symposium on VLSI Circuits, VLSIC 2012 (pp. 46-47). Article 6243782 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). https://doi.org/10.1109/VLSIC.2012.6243782

Ohsawa, T, Koike, H, Miura, S, Honjo, H, Tokutome, K, Ikeda, S, Hanyu, T, Ohno, H & Endoh, T 2012, 1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times. in 2012 Symposium on VLSI Circuits, VLSIC 2012., 6243782, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 46-47, 2012 Symposium on VLSI Circuits, VLSIC 2012, Honolulu, HI, United States, 12/6/13. https://doi.org/10.1109/VLSIC.2012.6243782

Ohsawa T, Koike H, Miura S, Honjo H, Tokutome K, Ikeda S その他. 1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times. In 2012 Symposium on VLSI Circuits, VLSIC 2012. 2012. p. 46-47. 6243782. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). doi: 10.1109/VLSIC.2012.6243782

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abstract = "A 1Mb nonvolatile STT-RAM using the 4T-2MTJ cell is designed and fabricated using 90nm CMOS and MTJ processes. 32 cells along a word line (WL) are simultaneously power-gated with quick wake-up/power-off times of 1.0ns/200ps, respectively, to reduce operation power and to eliminate standby power of the chip. The cell is experimentally shown to retain data with static noise margin (SNM) 0.32V under V dd=1V. The 1Mb chip with 2.19μm 2 cell is successfully operated with array access time of 8ns and read power of 10.7mW under 10ns cycle. The macro size of 1Mb STT-RAM is predicted to become smaller than the 1Mb 6T-SRAM in 45nm and beyond.",

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AU - Honjo, H.

AU - Tokutome, K.

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