@inproceedings{81e17a230b86480e8d56d2e1d50862c6,
title = "2.37-dBm-output 288-310 GHz frequency multiplier in 40 nm CMOS",
abstract = "We introduce a 288-310 GHz frequency multiplier fabricated with 40 nm CMOS technology. With 410.3 mW power consumption, this frequency multiplier has a conversion gain of 4.52 dB including that of its driver amplifier. The proposed system for input power/phase control of the power combiner enhances the output power of the frequency multiplier to 2.37 dBm at 300 GHz.",
keywords = "Bias optimization, Phase mismatch, Power combiner, Quad-ratrace",
author = "Kosuke Katayama and Kyoya Takano and Shuhei Amakawa and Takeshi Yoshida and Minoru Fujishima",
note = "Funding Information: ACKNOWLEDGMENT This work was supported by R&D on wireless transceiver systems with CMOS technology in 300GHz band, as part of the R&D program on key technology in terahertz frequency bands by the Ministry of Internal Affairs and Communications of Japan. Publisher Copyright: {\textcopyright} 2017 IEEE.; 2017 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2017 ; Conference date: 30-08-2017 Through 01-09-2017",
year = "2017",
month = sep,
day = "20",
doi = "10.1109/RFIT.2017.8048279",
language = "English",
series = "2017 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2017",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "28--30",
booktitle = "2017 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2017",
}