2D-PPC: A single-correction multiple-detection method for Through-Silicon-Via Faults

Khanh N. Dang; Michael Conrad Meyer; Akram Ben Ahmed; Abderazek Ben Abdallah; Xuan Tu Tran

doi:10.1109/APCCAS47518.2019.8953131

2D-PPC: A single-correction multiple-detection method for Through-Silicon-Via Faults

Khanh N. Dang^*, Michael Conrad Meyer, Akram Ben Ahmed, Abderazek Ben Abdallah, Xuan Tu Tran

^*この研究の対応する著者

情報生産システム研究センター

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

Through-Silicon-Via (TSV) is one of the most promising technologies to realize 3D Integrated Circuits (3D-ICs). However, the reliability issues due to the low yield rates, the sensitivity to thermal hotspots and stress issues due to the difference in temperature between layers are preventing TSV-based 3D-ICs from being widely and efficiently used. Due to defect clustering, 3D-ICs could have multiple defects in the same region which cannot be detected by using error correction codes while dedicated testing could take a significant number of testing cycles. This paper presents a 2D Parity Product Code (2D-PPC) with the ability to correct one fault and detect, at least, two faults. With the extension using Orthogonal Latin Square, 2D-PPC could detect multiple defects while reasonably increasing the area cost and latency.

本文言語	English
ホスト出版物のタイトル	Proceedings - APCCAS 2019
ホスト出版物のサブタイトル	2019 IEEE Asia Pacific Conference on Circuits and Systems: Innovative CAS Towards Sustainable Energy and Technology Disruption
出版社	Institute of Electrical and Electronics Engineers Inc.
ページ	109-112
ページ数	4
ISBN（電子版）	9781728129402
DOI	https://doi.org/10.1109/APCCAS47518.2019.8953131
出版ステータス	Published - 2019 11月
イベント	15th Annual IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2019 - Bangkok, Thailand 継続期間: 2019 11月 11 → 2019 11月 14

出版物シリーズ

名前	Proceedings - APCCAS 2019: 2019 IEEE Asia Pacific Conference on Circuits and Systems: Innovative CAS Towards Sustainable Energy and Technology Disruption

Conference

Conference	15th Annual IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2019
国/地域	Thailand
City	Bangkok
Period	19/11/11 → 19/11/14

ASJC Scopus subject areas

エネルギー工学および電力技術
再生可能エネルギー、持続可能性、環境
電子工学および電気工学
電子材料、光学材料、および磁性材料
器械工学

UN SDG

この成果は、次の持続可能な開発目標に貢献しています

文献へのアクセス

10.1109/APCCAS47518.2019.8953131

他のファイルとリンク

引用スタイル

Dang, K. N., Meyer, M. C., Ahmed, A. B., Abdallah, A. B., & Tran, X. T. (2019). 2D-PPC: A single-correction multiple-detection method for Through-Silicon-Via Faults. In Proceedings - APCCAS 2019: 2019 IEEE Asia Pacific Conference on Circuits and Systems: Innovative CAS Towards Sustainable Energy and Technology Disruption (pp. 109-112). Article 8953131 (Proceedings - APCCAS 2019: 2019 IEEE Asia Pacific Conference on Circuits and Systems: Innovative CAS Towards Sustainable Energy and Technology Disruption). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APCCAS47518.2019.8953131

2D-PPC: A single-correction multiple-detection method for Through-Silicon-Via Faults. / Dang, Khanh N.; Meyer, Michael Conrad; Ahmed, Akram Ben その他.
Proceedings - APCCAS 2019: 2019 IEEE Asia Pacific Conference on Circuits and Systems: Innovative CAS Towards Sustainable Energy and Technology Disruption. Institute of Electrical and Electronics Engineers Inc., 2019. p. 109-112 8953131 (Proceedings - APCCAS 2019: 2019 IEEE Asia Pacific Conference on Circuits and Systems: Innovative CAS Towards Sustainable Energy and Technology Disruption).

研究成果: Conference contribution

Dang, KN, Meyer, MC, Ahmed, AB, Abdallah, AB & Tran, XT 2019, 2D-PPC: A single-correction multiple-detection method for Through-Silicon-Via Faults. in Proceedings - APCCAS 2019: 2019 IEEE Asia Pacific Conference on Circuits and Systems: Innovative CAS Towards Sustainable Energy and Technology Disruption., 8953131, Proceedings - APCCAS 2019: 2019 IEEE Asia Pacific Conference on Circuits and Systems: Innovative CAS Towards Sustainable Energy and Technology Disruption, Institute of Electrical and Electronics Engineers Inc., pp. 109-112, 15th Annual IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2019, Bangkok, Thailand, 19/11/11. https://doi.org/10.1109/APCCAS47518.2019.8953131

Dang KN, Meyer MC, Ahmed AB, Abdallah AB, Tran XT. 2D-PPC: A single-correction multiple-detection method for Through-Silicon-Via Faults. In Proceedings - APCCAS 2019: 2019 IEEE Asia Pacific Conference on Circuits and Systems: Innovative CAS Towards Sustainable Energy and Technology Disruption. Institute of Electrical and Electronics Engineers Inc. 2019. p. 109-112. 8953131. (Proceedings - APCCAS 2019: 2019 IEEE Asia Pacific Conference on Circuits and Systems: Innovative CAS Towards Sustainable Energy and Technology Disruption). doi: 10.1109/APCCAS47518.2019.8953131

Dang, Khanh N. ; Meyer, Michael Conrad ; Ahmed, Akram Ben その他. / 2D-PPC : A single-correction multiple-detection method for Through-Silicon-Via Faults. Proceedings - APCCAS 2019: 2019 IEEE Asia Pacific Conference on Circuits and Systems: Innovative CAS Towards Sustainable Energy and Technology Disruption. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 109-112 (Proceedings - APCCAS 2019: 2019 IEEE Asia Pacific Conference on Circuits and Systems: Innovative CAS Towards Sustainable Energy and Technology Disruption).

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title = "2D-PPC: A single-correction multiple-detection method for Through-Silicon-Via Faults",

abstract = "Through-Silicon-Via (TSV) is one of the most promising technologies to realize 3D Integrated Circuits (3D-ICs). However, the reliability issues due to the low yield rates, the sensitivity to thermal hotspots and stress issues due to the difference in temperature between layers are preventing TSV-based 3D-ICs from being widely and efficiently used. Due to defect clustering, 3D-ICs could have multiple defects in the same region which cannot be detected by using error correction codes while dedicated testing could take a significant number of testing cycles. This paper presents a 2D Parity Product Code (2D-PPC) with the ability to correct one fault and detect, at least, two faults. With the extension using Orthogonal Latin Square, 2D-PPC could detect multiple defects while reasonably increasing the area cost and latency.",

keywords = "3D-ICs, Error Correction Code, Fault Tolerance, Orthogonal Latin Square, Through Silicon Via",

author = "Dang, {Khanh N.} and Meyer, {Michael Conrad} and Ahmed, {Akram Ben} and Abdallah, {Abderazek Ben} and Tran, {Xuan Tu}",

note = "Funding Information: This research is funded by Vietnam National Foundation for Science and Technology Development (NAFOSTED) under grant number 102.01-2018.312. Publisher Copyright: {\textcopyright} 2019 IEEE.; 15th Annual IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2019 ; Conference date: 11-11-2019 Through 14-11-2019",

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AU - Dang, Khanh N.

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AU - Tran, Xuan Tu

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AB - Through-Silicon-Via (TSV) is one of the most promising technologies to realize 3D Integrated Circuits (3D-ICs). However, the reliability issues due to the low yield rates, the sensitivity to thermal hotspots and stress issues due to the difference in temperature between layers are preventing TSV-based 3D-ICs from being widely and efficiently used. Due to defect clustering, 3D-ICs could have multiple defects in the same region which cannot be detected by using error correction codes while dedicated testing could take a significant number of testing cycles. This paper presents a 2D Parity Product Code (2D-PPC) with the ability to correct one fault and detect, at least, two faults. With the extension using Orthogonal Latin Square, 2D-PPC could detect multiple defects while reasonably increasing the area cost and latency.

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KW - Error Correction Code

KW - Fault Tolerance

KW - Orthogonal Latin Square

KW - Through Silicon Via

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2D-PPC: A single-correction multiple-detection method for Through-Silicon-Via Faults

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出版物シリーズ

Conference

ASJC Scopus subject areas

UN SDG

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