TY - GEN
T1 - 46% Peak PAE 28 GHz High Linearity Stacked-FET Power Amplifier IC with a Novel Two-Step Adaptive Bias Circuit in 45-nm SOI CMOS
AU - Sugiura, Tsuyoshi
AU - Yoshimasu, Toshihiko
N1 - Funding Information:
The authors would like to thank GlobalFoundries for chip fabrication and continuous support. The authors would also like to thank the VLSI Design and Education Center (VDEC), University of Tokyo in collaboration with Cadence Design Systems, Inc., Mentor Graphics, Inc., and Keysight Technologies Japan, Ltd.
Publisher Copyright:
© 2022 European Microwave Association (EuMA).
PY - 2022
Y1 - 2022
N2 - This paper presents a 28 GHz high linearity power amplifier (PA) IC with a novel two-step adaptively controlled bias circuit for 5th generation (5G) mobile terminal applications in a 45-nm silicon on insulator (SOI) CMOS process. The novel bias circuit adaptively controls the gate voltage of a stacked-FET by a step procedure to improve the 1dB compression point (P1dB) and efficiency in the several-dB back-off region. The PA employs a 3-stacked-FET structure to overcome the low breakdown voltage issue in scaled MOSFETs. At a supply voltage of 3.5 V, the fabricated PA exhibits a peak power added efficiency (PAE) of 46.0%, a saturated output power of 20.5 dBm, a 3 dB output power back-off efficiency of 35.2%, a 6 dB output power back-off efficiency of 26.0% and a small signal gain of 15.0 dB. The PA IC occupies only 0.23 mm2.
AB - This paper presents a 28 GHz high linearity power amplifier (PA) IC with a novel two-step adaptively controlled bias circuit for 5th generation (5G) mobile terminal applications in a 45-nm silicon on insulator (SOI) CMOS process. The novel bias circuit adaptively controls the gate voltage of a stacked-FET by a step procedure to improve the 1dB compression point (P1dB) and efficiency in the several-dB back-off region. The PA employs a 3-stacked-FET structure to overcome the low breakdown voltage issue in scaled MOSFETs. At a supply voltage of 3.5 V, the fabricated PA exhibits a peak power added efficiency (PAE) of 46.0%, a saturated output power of 20.5 dBm, a 3 dB output power back-off efficiency of 35.2%, a 6 dB output power back-off efficiency of 26.0% and a small signal gain of 15.0 dB. The PA IC occupies only 0.23 mm2.
KW - adaptive bias
KW - high back-off efficiency
KW - high linearity SOI CMOS
KW - stacked-FET
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U2 - 10.23919/EuMIC54520.2022.9923449
DO - 10.23919/EuMIC54520.2022.9923449
M3 - Conference contribution
AN - SCOPUS:85141827568
T3 - 2022 17th European Microwave Integrated Circuits Conference, EuMIC 2022
SP - 165
EP - 168
BT - 2022 17th European Microwave Integrated Circuits Conference, EuMIC 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 17th European Microwave Integrated Circuits Conference, EuMIC 2022
Y2 - 26 September 2022 through 27 September 2022
ER -