A 5. 4 mu m**2 stacked capacitor DRAM cell is realized using a quadruple-polysilicon gate structue and 0. 6 mu m pattern delineation technology. Memory operation in an experimental 4-Kbit array was successfully observed. A 5nm dielectric composite film and storage node pattern optimization by computer simulation are used to realize increased storage capacitance in this small cell. Charge retention characteristics and alpha particle immunity are favorable, indicating that this cell is a good candidate for application to 16 megabit DRAMs.
|ホスト出版物のタイトル||Conference on Solid State Devices and Materials|
|出版社||Japan Soc of Applied Physics|
|出版ステータス||Published - 1987|
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