60% Cycle time acceleration, 55% energy reduction, 32Kbit SRAM by auto-selective boost (ASB) scheme for slow memory cells in random variations

Yasue Yamamoto; Atsushi Kawasumi; Shinichi Moriwaki; Toshikazu Suzuki; Shinji Miyano; Hirofumi Shinohara

doi:10.1109/ESSCIRC.2012.6341318

60% Cycle time acceleration, 55% energy reduction, 32Kbit SRAM by auto-selective boost (ASB) scheme for slow memory cells in random variations

Yasue Yamamoto^*, Atsushi Kawasumi, Shinichi Moriwaki, Toshikazu Suzuki, Shinji Miyano, Hirofumi Shinohara

^*この研究の対応する著者

研究成果: Conference contribution

2 被引用数 (Scopus)

抄録

An auto selective boost (ASB) scheme for slow SRAM memory cells in random variations has been proposed. ASB shortens the cycle time and decreases the average BL amplitude, which reduces both dynamic and leakage energy dissipation. The cycle time of SRAM is reduced by 60% at 0.5V using the proposed ASB scheme. By combining the ASB with a BL amplitude limiter (BAL), the energy dissipation is reduced by 55%. A 32Kbit SRAM with the ASB and BAL schemes has been fabricated by 40nm CMOS technology.

本文言語	English
ホスト出版物のタイトル	2012 Proceedings of the European Solid State Circuits Conference, ESSCIRC 2012
ページ	317-320
ページ数	4
DOI	https://doi.org/10.1109/ESSCIRC.2012.6341318
出版ステータス	Published - 2012
外部発表	はい
イベント	38th European Solid State Circuits Conference, ESSCIRC 2012 - Bordeaux, France 継続期間: 2012 9月 17 → 2012 9月 21

出版物シリーズ

名前	European Solid-State Circuits Conference
ISSN（印刷版）	1930-8833

Other

Other	38th European Solid State Circuits Conference, ESSCIRC 2012
国/地域	France
City	Bordeaux
Period	12/9/17 → 12/9/21

ASJC Scopus subject areas

ハードウェアとアーキテクチャ
電子工学および電気工学

文献へのアクセス

10.1109/ESSCIRC.2012.6341318

他のファイルとリンク

フィンガープリント

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引用スタイル

Yamamoto, Y., Kawasumi, A., Moriwaki, S., Suzuki, T., Miyano, S., & Shinohara, H. (2012). 60% Cycle time acceleration, 55% energy reduction, 32Kbit SRAM by auto-selective boost (ASB) scheme for slow memory cells in random variations. In 2012 Proceedings of the European Solid State Circuits Conference, ESSCIRC 2012 (pp. 317-320). 記事 6341318 (European Solid-State Circuits Conference). https://doi.org/10.1109/ESSCIRC.2012.6341318

60% Cycle time acceleration, 55% energy reduction, 32Kbit SRAM by auto-selective boost (ASB) scheme for slow memory cells in random variations. / Yamamoto, Yasue; Kawasumi, Atsushi; Moriwaki, Shinichi その他.
2012 Proceedings of the European Solid State Circuits Conference, ESSCIRC 2012. 2012. p. 317-320 6341318 (European Solid-State Circuits Conference).

研究成果: Conference contribution

Yamamoto, Y, Kawasumi, A, Moriwaki, S, Suzuki, T, Miyano, S & Shinohara, H 2012, 60% Cycle time acceleration, 55% energy reduction, 32Kbit SRAM by auto-selective boost (ASB) scheme for slow memory cells in random variations. in 2012 Proceedings of the European Solid State Circuits Conference, ESSCIRC 2012., 6341318, European Solid-State Circuits Conference, pp. 317-320, 38th European Solid State Circuits Conference, ESSCIRC 2012, Bordeaux, France, 12/9/17. https://doi.org/10.1109/ESSCIRC.2012.6341318

Yamamoto Y, Kawasumi A, Moriwaki S, Suzuki T, Miyano S, Shinohara H. 60% Cycle time acceleration, 55% energy reduction, 32Kbit SRAM by auto-selective boost (ASB) scheme for slow memory cells in random variations. In 2012 Proceedings of the European Solid State Circuits Conference, ESSCIRC 2012. 2012. p. 317-320. 6341318. (European Solid-State Circuits Conference). doi: 10.1109/ESSCIRC.2012.6341318

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