60 ns 3.3 V 16 Mb DRAM

Kazutami Arimoto; Kazuyasu Fujishima; Yoshio Matsuda; Tsukasa Oishi; Masaki Tsukude; Wataru Wakamiya; Shin ichi Satoh; Michihiro Yamada; Tsutomu Yoshihara; Takao Nakano

60 ns 3.3 V 16 Mb DRAM

Kazutami Arimoto^*, Kazuyasu Fujishima, Yoshio Matsuda, Tsukasa Oishi, Masaki Tsukude, Wataru Wakamiya, Shin ichi Satoh, Michihiro Yamada, Tsutomu Yoshihara, Takao Nakano

^*この研究の対応する著者

研究成果: Conference contribution

11 被引用数 (Scopus)

抄録

The authors describe a single 3.3-V, 16-Mb DRAM (dynamic RAM) fabricated in a 0.5-μm, twin-well CMOS technology and packaged in a 400-mil small-outline J-leaded package. The design features are an array architecture based on the twisted-bit-line (TBL) technique and a multipurpose register (MPR) enabling an effective line mode test (LMT), copy write, and high-speed cache access capability. Under typical conditions at V _cc = 3.3 V, a row-address-strobe access time of 60 ns was obtained. Features of the RAM are summarized.

本文言語	English
ホスト出版物のタイトル	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
編集者	Anon
出版社	Publ by IEEE
ページ	244-245, 352
巻	32
出版ステータス	Published - 1989
外部発表	はい
イベント	IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 1989) - New York, NY, USA 継続期間: 1989 2月 15 → 1989 2月 17

Other

Other	IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 1989)
City	New York, NY, USA
Period	89/2/15 → 89/2/17

ASJC Scopus subject areas

ハードウェアとアーキテクチャ
電子工学および電気工学

他のファイルとリンク

引用スタイル

Arimoto, K, Fujishima, K, Matsuda, Y, Oishi, T, Tsukude, M, Wakamiya, W, Satoh, SI, Yamada, M, Yoshihara, T & Nakano, T 1989, 60 ns 3.3 V 16 Mb DRAM. in Anon (ed.), Digest of Technical Papers - IEEE International Solid-State Circuits Conference. vol. 32, Publ by IEEE, pp. 244-245, 352, IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 1989), New York, NY, USA, 89/2/15.

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title = "60 ns 3.3 V 16 Mb DRAM",

abstract = "The authors describe a single 3.3-V, 16-Mb DRAM (dynamic RAM) fabricated in a 0.5-μm, twin-well CMOS technology and packaged in a 400-mil small-outline J-leaded package. The design features are an array architecture based on the twisted-bit-line (TBL) technique and a multipurpose register (MPR) enabling an effective line mode test (LMT), copy write, and high-speed cache access capability. Under typical conditions at V cc = 3.3 V, a row-address-strobe access time of 60 ns was obtained. Features of the RAM are summarized. ",

author = "Kazutami Arimoto and Kazuyasu Fujishima and Yoshio Matsuda and Tsukasa Oishi and Masaki Tsukude and Wataru Wakamiya and Satoh, {Shin ichi} and Michihiro Yamada and Tsutomu Yoshihara and Takao Nakano",

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T1 - 60 ns 3.3 V 16 Mb DRAM

AU - Arimoto, Kazutami

AU - Fujishima, Kazuyasu

AU - Matsuda, Yoshio

AU - Oishi, Tsukasa

AU - Tsukude, Masaki

AU - Wakamiya, Wataru

AU - Satoh, Shin ichi

AU - Yamada, Michihiro

AU - Yoshihara, Tsutomu

AU - Nakano, Takao

PY - 1989

Y1 - 1989

N2 - The authors describe a single 3.3-V, 16-Mb DRAM (dynamic RAM) fabricated in a 0.5-μm, twin-well CMOS technology and packaged in a 400-mil small-outline J-leaded package. The design features are an array architecture based on the twisted-bit-line (TBL) technique and a multipurpose register (MPR) enabling an effective line mode test (LMT), copy write, and high-speed cache access capability. Under typical conditions at V cc = 3.3 V, a row-address-strobe access time of 60 ns was obtained. Features of the RAM are summarized.

AB - The authors describe a single 3.3-V, 16-Mb DRAM (dynamic RAM) fabricated in a 0.5-μm, twin-well CMOS technology and packaged in a 400-mil small-outline J-leaded package. The design features are an array architecture based on the twisted-bit-line (TBL) technique and a multipurpose register (MPR) enabling an effective line mode test (LMT), copy write, and high-speed cache access capability. Under typical conditions at V cc = 3.3 V, a row-address-strobe access time of 60 ns was obtained. Features of the RAM are summarized.

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M3 - Conference contribution

AN - SCOPUS:0024943742

VL - 32

SP - 244-245, 352

BT - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

A2 - Anon, null

PB - Publ by IEEE

T2 - IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 1989)

Y2 - 15 February 1989 through 17 February 1989

ER -

60 ns 3.3 V 16 Mb DRAM

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Other

ASJC Scopus subject areas

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