70 nm SOI-CMOS of 135 GHz fmax with dual offset-implanted source-drain extension structure for RF/analog and logic applications

T. Matsumoto; S. Maeda; K. Ota; Y. Hirano; K. Eikyu; H. Sayama; T. Iwamatsu; K. Yamamoto; T. Katoh; Y. Yamaguchi; T. Ipposhi; H. Oda; S. Maegawa; Y. Inoue; M. Inuishi

70 nm SOI-CMOS of 135 GHz f_max with dual offset-implanted source-drain extension structure for RF/analog and logic applications

T. Matsumoto, S. Maeda, K. Ota, Y. Hirano, K. Eikyu, H. Sayama, T. Iwamatsu, K. Yamamoto^*, T. Katoh, Y. Yamaguchi, T. Ipposhi, H. Oda, S. Maegawa, Y. Inoue, M. Inuishi

^*この研究の対応する著者

研究成果: Conference article › 査読

23 被引用数 (Scopus)

抄録

We achieved 135 GHz f_max and 10.98 dB MSG at 40 GHz, which represent the world record data in CMOS published papers, by using a 70 nm body-tied partially-depleted (PD) SOI-CMOS with offset-implanted source-drain extension (SDE) and thick cobalt salicide. The suppression of V_th variations was also realized due to this structure. Dual offset-implanted SDE structure was proposed to realize high performance of both RF/analog and logic applications. We found that the optimized offset gate spacer width of the RF/analog parts is different from that of the logic parts.

本文言語	English
ページ（範囲）	219-222
ページ数	4
ジャーナル	Technical Digest - International Electron Devices Meeting
出版ステータス	Published - 2001
外部発表	はい
イベント	IEEE International Electron Devices Meeting IEDM 2001 - Washington, DC, United States 継続期間: 2001 12月 2 → 2001 12月 5

ASJC Scopus subject areas

電子材料、光学材料、および磁性材料
凝縮系物理学
電子工学および電気工学
材料化学

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引用スタイル

Matsumoto, T., Maeda, S., Ota, K., Hirano, Y., Eikyu, K., Sayama, H., Iwamatsu, T., Yamamoto, K., Katoh, T., Yamaguchi, Y., Ipposhi, T., Oda, H., Maegawa, S., Inoue, Y., & Inuishi, M. (2001). 70 nm SOI-CMOS of 135 GHz f_max with dual offset-implanted source-drain extension structure for RF/analog and logic applications. Technical Digest - International Electron Devices Meeting, 219-222.

Matsumoto, T, Maeda, S, Ota, K, Hirano, Y, Eikyu, K, Sayama, H, Iwamatsu, T, Yamamoto, K, Katoh, T, Yamaguchi, Y, Ipposhi, T, Oda, H, Maegawa, S, Inoue, Y & Inuishi, M 2001, '70 nm SOI-CMOS of 135 GHz f_max with dual offset-implanted source-drain extension structure for RF/analog and logic applications', Technical Digest - International Electron Devices Meeting, pp. 219-222.

@article{2dd62b262a654a3b8bdaba4f411c3dc1,

title = "70 nm SOI-CMOS of 135 GHz fmax with dual offset-implanted source-drain extension structure for RF/analog and logic applications",

abstract = "We achieved 135 GHz fmax and 10.98 dB MSG at 40 GHz, which represent the world record data in CMOS published papers, by using a 70 nm body-tied partially-depleted (PD) SOI-CMOS with offset-implanted source-drain extension (SDE) and thick cobalt salicide. The suppression of Vth variations was also realized due to this structure. Dual offset-implanted SDE structure was proposed to realize high performance of both RF/analog and logic applications. We found that the optimized offset gate spacer width of the RF/analog parts is different from that of the logic parts.",

author = "T. Matsumoto and S. Maeda and K. Ota and Y. Hirano and K. Eikyu and H. Sayama and T. Iwamatsu and K. Yamamoto and T. Katoh and Y. Yamaguchi and T. Ipposhi and H. Oda and S. Maegawa and Y. Inoue and M. Inuishi",

year = "2001",

language = "English",

pages = "219--222",

journal = "Technical Digest - International Electron Devices Meeting",

issn = "0163-1918",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "IEEE International Electron Devices Meeting IEDM 2001 ; Conference date: 02-12-2001 Through 05-12-2001",

}

TY - JOUR

T1 - 70 nm SOI-CMOS of 135 GHz fmax with dual offset-implanted source-drain extension structure for RF/analog and logic applications

AU - Matsumoto, T.

AU - Maeda, S.

AU - Ota, K.

AU - Hirano, Y.

AU - Eikyu, K.

AU - Sayama, H.

AU - Iwamatsu, T.

AU - Yamamoto, K.

AU - Katoh, T.

AU - Yamaguchi, Y.

AU - Ipposhi, T.

AU - Oda, H.

AU - Maegawa, S.

AU - Inoue, Y.

AU - Inuishi, M.

PY - 2001

Y1 - 2001

N2 - We achieved 135 GHz fmax and 10.98 dB MSG at 40 GHz, which represent the world record data in CMOS published papers, by using a 70 nm body-tied partially-depleted (PD) SOI-CMOS with offset-implanted source-drain extension (SDE) and thick cobalt salicide. The suppression of Vth variations was also realized due to this structure. Dual offset-implanted SDE structure was proposed to realize high performance of both RF/analog and logic applications. We found that the optimized offset gate spacer width of the RF/analog parts is different from that of the logic parts.

AB - We achieved 135 GHz fmax and 10.98 dB MSG at 40 GHz, which represent the world record data in CMOS published papers, by using a 70 nm body-tied partially-depleted (PD) SOI-CMOS with offset-implanted source-drain extension (SDE) and thick cobalt salicide. The suppression of Vth variations was also realized due to this structure. Dual offset-implanted SDE structure was proposed to realize high performance of both RF/analog and logic applications. We found that the optimized offset gate spacer width of the RF/analog parts is different from that of the logic parts.

UR - http://www.scopus.com/inward/record.url?scp=18144443346&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=18144443346&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:18144443346

SN - 0163-1918

SP - 219

EP - 222

JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

T2 - IEEE International Electron Devices Meeting IEDM 2001

Y2 - 2 December 2001 through 5 December 2001

ER -