A 100-MHz 4-Mb cache DRAM with fast copy-back scheme

Katsumi Dosaka; Yasuhiro Konishi; Kouji Hayano; Katsumitsu Himukashi; Akira Yamazaki; Hisashi Iwamoto; Masaki Kumanoya; Hisanori Hamano; Tsutomu Yoshihara

doi:10.1109/4.165333

A 100-MHz 4-Mb cache DRAM with fast copy-back scheme

Katsumi Dosaka^*, Yasuhiro Konishi, Kouji Hayano, Katsumitsu Himukashi, Akira Yamazaki, Hisashi Iwamoto, Masaki Kumanoya, Hisanori Hamano, Tsutomu Yoshihara

^*この研究の対応する著者

研究成果: Article › 査読

10 被引用数 (Scopus)

抄録

A 4-Mb cache dynamic random access memory (CDRAM), which integrates 16-kb SRAM as a cache memory and 4-Mb DRAM into a monolithic circuit, is described. This CDRAM has a 100-MHz operating cache, newly proposed fast copy-back (FCB) scheme that realizes a three times faster miss access time over with the conventional copy-back method, and maximized mapping flexibility. The process technology is a quad-polysilicon double-metal 0.7-μm CMOS process, which is the same as used in a conventional 4-Mb DRAM. The chip size of 82.9 mm² is only a 7% increase over the conventional 4-MB DRAM. The simulated system performance indicated better performance than a conventional cache system with eight times the cache capacity.

本文言語	English
ページ（範囲）	1534-1539
ページ数	6
ジャーナル	IEEE Journal of Solid-State Circuits
巻	27
号	11
DOI	https://doi.org/10.1109/4.165333
出版ステータス	Published - 1992 11月
外部発表	はい

ASJC Scopus subject areas

電子工学および電気工学

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10.1109/4.165333

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引用スタイル

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AU - Dosaka, Katsumi

AU - Konishi, Yasuhiro

AU - Hayano, Kouji

AU - Himukashi, Katsumitsu

AU - Yamazaki, Akira

AU - Iwamoto, Hisashi

AU - Kumanoya, Masaki

AU - Hamano, Hisanori

AU - Yoshihara, Tsutomu

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N2 - A 4-Mb cache dynamic random access memory (CDRAM), which integrates 16-kb SRAM as a cache memory and 4-Mb DRAM into a monolithic circuit, is described. This CDRAM has a 100-MHz operating cache, newly proposed fast copy-back (FCB) scheme that realizes a three times faster miss access time over with the conventional copy-back method, and maximized mapping flexibility. The process technology is a quad-polysilicon double-metal 0.7-μm CMOS process, which is the same as used in a conventional 4-Mb DRAM. The chip size of 82.9 mm2 is only a 7% increase over the conventional 4-MB DRAM. The simulated system performance indicated better performance than a conventional cache system with eight times the cache capacity.

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A 100-MHz 4-Mb cache DRAM with fast copy-back scheme

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