TY - GEN
T1 - A 1080p@60fps multi-standard video decoder chip designed for power and cost efficiency in a system perspective
AU - Zhou, Dajiang
AU - You, Zongyuan
AU - Zhu, Jiayi
AU - Kong, Ji
AU - Hong, Yu
AU - Chen, Xianmin
AU - He, Xuewen
AU - Xu, Chen
AU - Zhang, Hang
AU - Zhou, Jinjia
AU - Deng, Ning
AU - Liu, Peilin
AU - Goto, Satoshi
PY - 2009
Y1 - 2009
N2 - In this paper, we present a video decoder chip for H.264/AVC high profile, MPEG-1/2 main profile and AVS Jprofile, which is capable of 60fps 1080p decoding at 200MHz. By applying a dedicated DRAM sub-system and a 2-D cache architecture, 50% of pins for DRAM connection and 36% of power consumption are saved, compared to state-of-the-art work in a system perspective. Meanwhile, 38% of gate count is reduced by applying resource sharing architectures between the 3 supported video formats.
AB - In this paper, we present a video decoder chip for H.264/AVC high profile, MPEG-1/2 main profile and AVS Jprofile, which is capable of 60fps 1080p decoding at 200MHz. By applying a dedicated DRAM sub-system and a 2-D cache architecture, 50% of pins for DRAM connection and 36% of power consumption are saved, compared to state-of-the-art work in a system perspective. Meanwhile, 38% of gate count is reduced by applying resource sharing architectures between the 3 supported video formats.
UR - http://www.scopus.com/inward/record.url?scp=70449365306&partnerID=8YFLogxK
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M3 - Conference contribution
AN - SCOPUS:70449365306
SN - 9784863480018
SP - 262
EP - 263
BT - IEEE Symposium on VLSI Circuits, Digest of Technical Papers
T2 - 2009 Symposium on VLSI Circuits
Y2 - 16 June 2009 through 18 June 2009
ER -