TY - GEN
T1 - A 14-GHz-Band Harmonic Tuned Low-Power Low-Phase-Noise VCO IC with a Novel Bias Feedback Circuit in 40-nm CMOS SOI
AU - Fang, Mengchu
AU - Yoshimasu, Toshihiko
N1 - Funding Information:
ACKNOWLEDGMENT The authors would like to thank GlobalFoundries for chip fabrication. This work is supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Cadence Design Systems, Inc., Mentor Graphics, Inc., and Keysight Technologies Japan, Ltd.
Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - In this paper, a harmonic tuned low-power low-phase-noise VCO IC with a novel bias feedback circuit is proposed. The transformer-based LC tank providing high impedance at the second and third harmonics is used to improve the phase noise performance. In addition, a novel feedback circuit is designed to suppress the gate-to-source voltage of the core transistors under their threshold voltage at the steady state while guaranteeing the robust start-up of the oscillation. The novel feedback circuit that requires no dc power supply can operate with an extremely small additional dc power consumption. The proposed VCO IC is designed, fabricated, and fully evaluated on-wafer in 40-nm CMOS SOI process. The proposed VCO IC has exhibited a measured best phase noise of-131.8 dBc/Hz at 10-MHz offset from the oscillation frequency of 14.94 GHz under a dc power consumption of only 1.4 mW.
AB - In this paper, a harmonic tuned low-power low-phase-noise VCO IC with a novel bias feedback circuit is proposed. The transformer-based LC tank providing high impedance at the second and third harmonics is used to improve the phase noise performance. In addition, a novel feedback circuit is designed to suppress the gate-to-source voltage of the core transistors under their threshold voltage at the steady state while guaranteeing the robust start-up of the oscillation. The novel feedback circuit that requires no dc power supply can operate with an extremely small additional dc power consumption. The proposed VCO IC is designed, fabricated, and fully evaluated on-wafer in 40-nm CMOS SOI process. The proposed VCO IC has exhibited a measured best phase noise of-131.8 dBc/Hz at 10-MHz offset from the oscillation frequency of 14.94 GHz under a dc power consumption of only 1.4 mW.
KW - CMOS SOI
KW - VCO IC
KW - feedback
KW - harmonics
KW - low power
KW - phase noise
UR - http://www.scopus.com/inward/record.url?scp=85137742033&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85137742033&partnerID=8YFLogxK
U2 - 10.1109/RFIC54546.2022.9863193
DO - 10.1109/RFIC54546.2022.9863193
M3 - Conference contribution
AN - SCOPUS:85137742033
T3 - Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
SP - 167
EP - 170
BT - 2022 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2022 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2022
Y2 - 19 June 2022 through 21 June 2022
ER -