TY - GEN
T1 - A 1.41 W H.264/AVC real-time encoder soc for HDTV1080P
AU - Liu, Zhenyu
AU - Song, Yang
AU - Shao, Ming
AU - Li, Shen
AU - Li, Ngfeng
AU - Ishiwata, Shunichi
AU - Nakagawa, Masaki
AU - Goto, Satoshi
AU - Ikenaga, Takeshi
PY - 2007/12/1
Y1 - 2007/12/1
N2 - A H.264/AVC baseline-profile real-time encoder for HDTV-1080p at 30fps is implemented with the dedicated hardware engines and one 32-bit Media embedded Processor (MeP) equipped with hardware extensions. The 11.5Gbps 64Mb System-in-Silicon DRAMA is embedded to alleviate the external memory bandwidth. With TSMC 0.1.8μm CMOS technology, the SoC core occupies 27.1 mm2 die area and consumes 1.41W at 200MHz in typical work conditions.
AB - A H.264/AVC baseline-profile real-time encoder for HDTV-1080p at 30fps is implemented with the dedicated hardware engines and one 32-bit Media embedded Processor (MeP) equipped with hardware extensions. The 11.5Gbps 64Mb System-in-Silicon DRAMA is embedded to alleviate the external memory bandwidth. With TSMC 0.1.8μm CMOS technology, the SoC core occupies 27.1 mm2 die area and consumes 1.41W at 200MHz in typical work conditions.
UR - http://www.scopus.com/inward/record.url?scp=39749203476&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=39749203476&partnerID=8YFLogxK
U2 - 10.1109/VLSIC.2007.4342716
DO - 10.1109/VLSIC.2007.4342716
M3 - Conference contribution
AN - SCOPUS:39749203476
SN - 9784900784048
T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers
SP - 12
EP - 13
BT - 2007 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
T2 - 2007 Symposium on VLSI Circuits, VLSIC
Y2 - 14 June 2007 through 16 June 2007
ER -