This paper proposes a 15-bit 10-MS/s pipelined ADC. To implement the incomplete settling principle, the traditional complete settling stage is improved to the incomplete settling structure through dividing the sampling clock of the traditional stage into two parts for discharging the sampling and feedback capacitors and completing the sampling, respectively. It verifies the correction and validity of optimizing ADCs' conversion speed without increasing power consumption through the incomplete settling. It is processed in 0.18μm 1P6M CMOS mixed-mode technology. Simulation results show that 82dB SNDR and 87dB SFDR are obtained at the sampling rate of 10MHz with the input sine frequency of 100KHz and the whole static power dissipation is 21.94mW.
|ホスト出版物のタイトル||2006 International Conference on Communications, Circuits and Systems, ICCCAS, Proceedings|
|出版ステータス||Published - 2006|
|イベント||2006 International Conference on Communications, Circuits and Systems, ICCCAS - Guilin|
継続期間: 2006 6月 25 → 2006 6月 28
|Other||2006 International Conference on Communications, Circuits and Systems, ICCCAS|
|Period||06/6/25 → 06/6/28|
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