A 15-bit 10-msample/s pipelined A/D converter based on incomplete settling principle

Shuaiqi Wang; Fule Li; Yasuaki Inoue

doi:10.1109/ICCCAS.2006.285108

A 15-bit 10-msample/s pipelined A/D converter based on incomplete settling principle

Shuaiqi Wang^*, Fule Li, Yasuaki Inoue

^*この研究の対応する著者

研究成果: Conference contribution

抄録

This paper proposes a 15-bit 10-MS/s pipelined ADC. To implement the incomplete settling principle, the traditional complete settling stage is improved to the incomplete settling structure through dividing the sampling clock of the traditional stage into two parts for discharging the sampling and feedback capacitors and completing the sampling, respectively. It verifies the correction and validity of optimizing ADCs' conversion speed without increasing power consumption through the incomplete settling. It is processed in 0.18μm 1P6M CMOS mixed-mode technology. Simulation results show that 82dB SNDR and 87dB SFDR are obtained at the sampling rate of 10MHz with the input sine frequency of 100KHz and the whole static power dissipation is 21.94mW.

本文言語	English
ホスト出版物のタイトル	2006 International Conference on Communications, Circuits and Systems, ICCCAS, Proceedings
ページ	2176-2180
ページ数	5
巻	4
DOI	https://doi.org/10.1109/ICCCAS.2006.285108
出版ステータス	Published - 2006
イベント	2006 International Conference on Communications, Circuits and Systems, ICCCAS - Guilin 継続期間: 2006 6月 25 → 2006 6月 28

Other

Other	2006 International Conference on Communications, Circuits and Systems, ICCCAS
City	Guilin
Period	06/6/25 → 06/6/28

ASJC Scopus subject areas

電子工学および電気工学

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10.1109/ICCCAS.2006.285108

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引用スタイル

Wang, S, Li, F & Inoue, Y 2006, A 15-bit 10-msample/s pipelined A/D converter based on incomplete settling principle. in 2006 International Conference on Communications, Circuits and Systems, ICCCAS, Proceedings. vol. 4, 4064355, pp. 2176-2180, 2006 International Conference on Communications, Circuits and Systems, ICCCAS, Guilin, 06/6/25. https://doi.org/10.1109/ICCCAS.2006.285108

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abstract = "This paper proposes a 15-bit 10-MS/s pipelined ADC. To implement the incomplete settling principle, the traditional complete settling stage is improved to the incomplete settling structure through dividing the sampling clock of the traditional stage into two parts for discharging the sampling and feedback capacitors and completing the sampling, respectively. It verifies the correction and validity of optimizing ADCs' conversion speed without increasing power consumption through the incomplete settling. It is processed in 0.18μm 1P6M CMOS mixed-mode technology. Simulation results show that 82dB SNDR and 87dB SFDR are obtained at the sampling rate of 10MHz with the input sine frequency of 100KHz and the whole static power dissipation is 21.94mW.",

author = "Shuaiqi Wang and Fule Li and Yasuaki Inoue",

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doi = "10.1109/ICCCAS.2006.285108",

language = "English",

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AU - Wang, Shuaiqi

AU - Li, Fule

AU - Inoue, Yasuaki

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Y1 - 2006

N2 - This paper proposes a 15-bit 10-MS/s pipelined ADC. To implement the incomplete settling principle, the traditional complete settling stage is improved to the incomplete settling structure through dividing the sampling clock of the traditional stage into two parts for discharging the sampling and feedback capacitors and completing the sampling, respectively. It verifies the correction and validity of optimizing ADCs' conversion speed without increasing power consumption through the incomplete settling. It is processed in 0.18μm 1P6M CMOS mixed-mode technology. Simulation results show that 82dB SNDR and 87dB SFDR are obtained at the sampling rate of 10MHz with the input sine frequency of 100KHz and the whole static power dissipation is 21.94mW.

AB - This paper proposes a 15-bit 10-MS/s pipelined ADC. To implement the incomplete settling principle, the traditional complete settling stage is improved to the incomplete settling structure through dividing the sampling clock of the traditional stage into two parts for discharging the sampling and feedback capacitors and completing the sampling, respectively. It verifies the correction and validity of optimizing ADCs' conversion speed without increasing power consumption through the incomplete settling. It is processed in 0.18μm 1P6M CMOS mixed-mode technology. Simulation results show that 82dB SNDR and 87dB SFDR are obtained at the sampling rate of 10MHz with the input sine frequency of 100KHz and the whole static power dissipation is 21.94mW.

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BT - 2006 International Conference on Communications, Circuits and Systems, ICCCAS, Proceedings

T2 - 2006 International Conference on Communications, Circuits and Systems, ICCCAS

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A 15-bit 10-msample/s pipelined A/D converter based on incomplete settling principle

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