抄録
A motion estimation (ME) processor for H.264 encoder is implemented in 40nm CMOS. With algorithm and architecture co-optimization, its throughput reaches 1.59Gpixel/s for 7680×4320p 48fps video, at least 7.5 times faster than previous chips. Its core power dissipation is 622mW at 210MHz, with energy efficiency improved by 23%. DRAM bandwidth requirement is reduced by 68%. With a maximum search range of ±211 (horizontal) by ±106 (vertical) around a predictive search center, the proposed ME processor well accommodates the large motion of ultra-high-resolution video.
| 本文言語 | English |
|---|---|
| ホスト出版物のタイトル | IEEE Symposium on VLSI Circuits, Digest of Technical Papers |
| 出版ステータス | Published - 2013 |
| イベント | 2013 Symposium on VLSI Circuits, VLSIC 2013 - Kyoto, Japan 継続期間: 2013 6月 12 → 2013 6月 14 |
Other
| Other | 2013 Symposium on VLSI Circuits, VLSIC 2013 |
|---|---|
| 国/地域 | Japan |
| City | Kyoto |
| Period | 13/6/12 → 13/6/14 |
ASJC Scopus subject areas
- 電子工学および電気工学
- 電子材料、光学材料、および磁性材料
UN SDG
この成果は、次の持続可能な開発目標に貢献しています
