A 160MHz 4-bit pipeline multiplier using charge recovery logic technology

Yimeng Zhang; Leona Okamura; Nan Wang; Tsutomu Yoshihara

doi:10.1109/SOCDC.2010.5682955

A 160MHz 4-bit pipeline multiplier using charge recovery logic technology

Yimeng Zhang^*, Leona Okamura, Nan Wang, Tsutomu Yoshihara

^*この研究の対応する著者

研究成果: Conference contribution

抄録

In this paper a 4-bit pipeline multiplier is designed using a novel charge-recovery logic technology called Pulse Boost Logic (PBL), and fabricated out with Rohm 0.18μm CMOS process. Cadence Spectre simulation indicates that energy dissipation of proposed PBL multiplier is 79% of Enhanced Boost Logic with almost the same number of transistors. The test chip is using a LC resonant system for AC power supply, since PBL structure requires two phase non-overlap clock as power supply. The measurement result shows that operation frequency of PBL 4-bit pipeline multiplier is up to 161MHz, while the energy dissipation is 4.81pJ/cycle.

本文言語	English
ホスト出版物のタイトル	2010 International SoC Design Conference, ISOCC 2010
ページ	127-130
ページ数	4
DOI	https://doi.org/10.1109/SOCDC.2010.5682955
出版ステータス	Published - 2010
イベント	2010 International SoC Design Conference, ISOCC 2010 - Incheon 継続期間: 2010 11月 22 → 2010 11月 23

Other

Other	2010 International SoC Design Conference, ISOCC 2010
City	Incheon
Period	10/11/22 → 10/11/23

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10.1109/SOCDC.2010.5682955

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title = "A 160MHz 4-bit pipeline multiplier using charge recovery logic technology",

abstract = "In this paper a 4-bit pipeline multiplier is designed using a novel charge-recovery logic technology called Pulse Boost Logic (PBL), and fabricated out with Rohm 0.18μm CMOS process. Cadence Spectre simulation indicates that energy dissipation of proposed PBL multiplier is 79% of Enhanced Boost Logic with almost the same number of transistors. The test chip is using a LC resonant system for AC power supply, since PBL structure requires two phase non-overlap clock as power supply. The measurement result shows that operation frequency of PBL 4-bit pipeline multiplier is up to 161MHz, while the energy dissipation is 4.81pJ/cycle.",

author = "Yimeng Zhang and Leona Okamura and Nan Wang and Tsutomu Yoshihara",

year = "2010",

doi = "10.1109/SOCDC.2010.5682955",

language = "English",

isbn = "9781424486335",

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AU - Zhang, Yimeng

AU - Okamura, Leona

AU - Wang, Nan

AU - Yoshihara, Tsutomu

PY - 2010

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N2 - In this paper a 4-bit pipeline multiplier is designed using a novel charge-recovery logic technology called Pulse Boost Logic (PBL), and fabricated out with Rohm 0.18μm CMOS process. Cadence Spectre simulation indicates that energy dissipation of proposed PBL multiplier is 79% of Enhanced Boost Logic with almost the same number of transistors. The test chip is using a LC resonant system for AC power supply, since PBL structure requires two phase non-overlap clock as power supply. The measurement result shows that operation frequency of PBL 4-bit pipeline multiplier is up to 161MHz, while the energy dissipation is 4.81pJ/cycle.

AB - In this paper a 4-bit pipeline multiplier is designed using a novel charge-recovery logic technology called Pulse Boost Logic (PBL), and fabricated out with Rohm 0.18μm CMOS process. Cadence Spectre simulation indicates that energy dissipation of proposed PBL multiplier is 79% of Enhanced Boost Logic with almost the same number of transistors. The test chip is using a LC resonant system for AC power supply, since PBL structure requires two phase non-overlap clock as power supply. The measurement result shows that operation frequency of PBL 4-bit pipeline multiplier is up to 161MHz, while the energy dissipation is 4.81pJ/cycle.

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DO - 10.1109/SOCDC.2010.5682955

M3 - Conference contribution

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SN - 9781424486335

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EP - 130

BT - 2010 International SoC Design Conference, ISOCC 2010

T2 - 2010 International SoC Design Conference, ISOCC 2010

Y2 - 22 November 2010 through 23 November 2010

ER -

A 160MHz 4-bit pipeline multiplier using charge recovery logic technology

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