A 24-b 50-ns Digital Image Signal Processor

Shin Ichi Nakagawa, Tetsuya Matsumura, Hiroshi Segawa, Masahiko Yoshimoto, Hirofumi Shinohara, Shu Ichi Kato, Masahiro Hatanaka, Yasutaka Horiba

研究成果: Article査読

3 被引用数 (Scopus)


This paper will report a 50-ns digital image signal processor (DISP), excellently suited for picture coding. The chip integrates 538K transistors and dissipates 1.4 W at 40-MHz clock. It is based on a 24-b fixed-point architecture with a five-stage pipeline. The instruction cycle time is 35 ns typically and 50 ns at worst. The DISP features a real-time processing capability realized by an enhanced parallel architecture, video-oriented data processing functions, and a 50-ns instruction cycle time at worst. Its 50-ns cycle time allows it to execute more than 60-million operations per second (MOPS). High-density 1.0-μm CMOS technology allows numerous on-chip features, which include specified resources optimized for the image processing. This enables a flexible hardware implementation of various algorithms for the picture coding. Several circuit design techniques to attain the fast instruction cycle include a distributed instruction decoding and a hierarchical clocking circuit. The LSI has been designed by the extensive use of a cell-based design method. The processor incorporates a sophisticated testing function compatible with the cell-based design environment. This paper will also discuss system performance advantages in the image/ video processing including the picture coding.

ジャーナルIEEE Journal of Solid-State Circuits
出版ステータスPublished - 1990 12月

ASJC Scopus subject areas

  • 電子工学および電気工学


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