A 250 mV bit-line swing scheme for 1-v operating gigabit scale drams

Tsuneo Inaba*, Daisaburo Takashima, Yukihito Oowaki, Tohru Ozaklt, Shigeyoshi Watanabe, Takashi Ohsawa, Kazunorî Ohuchi, Hiroyuki Tango


研究成果: Article査読


This paper proposes a small 1/4 Vcc bit-line swing scheme and a related sense amplifier scheme for low power 1 V operating DRAM. Using the proposed small bit-line swing scheme, the stress bias of memory cell transistor and capacitor is reduced to half that of the conventional DRAM, resulting in improvement of device reliability. The proposed sense amplifier scheme achieves high speed and stable sensing/restoring operation at 250mV bit-line swing, which is much smaller than threshold voltage. The proposed scheme reduces the total power dissipation of bit-line sensing/restoring operation to 40% of the conventional one. This paper also proposes a small 4F2 size memory cell and a new twisted bit-line scheme. The array noise is reduced to 8.6% of the conventional DRAM.

ジャーナルIEICE Transactions on Electronics
出版ステータスPublished - 1996 1月 1

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学


「A 250 mV bit-line swing scheme for 1-v operating gigabit scale drams」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。