A 26-GHz-band high back-off efficiency stacked-FET power amplifier IC with adaptively controlled bias and load circuits in 45-nm CMOS SOI

Toshihiko Yoshimasu; Mengchu Fang; Tsuyoshi Sugiura

doi:10.1587/transfun.2020GCP0012

A 26-GHz-band high back-off efficiency stacked-FET power amplifier IC with adaptively controlled bias and load circuits in 45-nm CMOS SOI

Toshihiko Yoshimasu^*, Mengchu Fang, Tsuyoshi Sugiura

^*この研究の対応する著者

研究成果: Article › 査読

1 被引用数 (Scopus)

抄録

This paper presents a 26-GHz-band high back-off efficiency power amplifier (PA) IC with adaptively controlled bias and load circuits in 45-nm CMOS SOI. A 4-stacked-FET is employed to increase the output power and to conquer the low breakdown voltage issue of scaled MOSFET. The adaptive bias circuit is reviewed and the adaptive load circuit which consists of an inverter circuit and transformer-based inductors is described in detail. The measured performance of the PA IC is fully shown in this paper. The PA IC exhibits a saturated output power of 20.5 dBm and a peak power-added-efficiency (PAE) as high as 39.4% at a supply voltage of 4.0 V. Moreover, the PA IC has exhibited an excellent ITRS FoM of 82.0 dB.

本文言語	English
ページ（範囲）	477-483
ページ数	7
ジャーナル	IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
巻	E104A
号	2
DOI	https://doi.org/10.1587/transfun.2020GCP0012
出版ステータス	Published - 2021 2月 1

ASJC Scopus subject areas

信号処理
コンピュータグラフィックスおよびコンピュータ支援設計
電子工学および電気工学
応用数学

文献へのアクセス

10.1587/transfun.2020GCP0012

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引用スタイル

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abstract = "This paper presents a 26-GHz-band high back-off efficiency power amplifier (PA) IC with adaptively controlled bias and load circuits in 45-nm CMOS SOI. A 4-stacked-FET is employed to increase the output power and to conquer the low breakdown voltage issue of scaled MOSFET. The adaptive bias circuit is reviewed and the adaptive load circuit which consists of an inverter circuit and transformer-based inductors is described in detail. The measured performance of the PA IC is fully shown in this paper. The PA IC exhibits a saturated output power of 20.5 dBm and a peak power-added-efficiency (PAE) as high as 39.4% at a supply voltage of 4.0 V. Moreover, the PA IC has exhibited an excellent ITRS FoM of 82.0 dB.",

keywords = "Adaptive bias, Adaptive load, CMOS SOI, High back-off efficiency, Stacked-FET",

author = "Toshihiko Yoshimasu and Mengchu Fang and Tsuyoshi Sugiura",

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AU - Sugiura, Tsuyoshi

N1 - Funding Information: The authors would like to thank GLOBALFOUNDRIES for chip fabrication and continuous support. This work is supported by VLSI Design and Education Center (VDEC), Uni- versity of Tokyo in collaboration with Cadence Design Systems, Inc., Menter Graphics, Inc., and Keysight Technologies Japan, Ltd. Publisher Copyright: Copyright © 2021 The Institute of Electronics, Information and Communication Engineers

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N2 - This paper presents a 26-GHz-band high back-off efficiency power amplifier (PA) IC with adaptively controlled bias and load circuits in 45-nm CMOS SOI. A 4-stacked-FET is employed to increase the output power and to conquer the low breakdown voltage issue of scaled MOSFET. The adaptive bias circuit is reviewed and the adaptive load circuit which consists of an inverter circuit and transformer-based inductors is described in detail. The measured performance of the PA IC is fully shown in this paper. The PA IC exhibits a saturated output power of 20.5 dBm and a peak power-added-efficiency (PAE) as high as 39.4% at a supply voltage of 4.0 V. Moreover, the PA IC has exhibited an excellent ITRS FoM of 82.0 dB.

AB - This paper presents a 26-GHz-band high back-off efficiency power amplifier (PA) IC with adaptively controlled bias and load circuits in 45-nm CMOS SOI. A 4-stacked-FET is employed to increase the output power and to conquer the low breakdown voltage issue of scaled MOSFET. The adaptive bias circuit is reviewed and the adaptive load circuit which consists of an inverter circuit and transformer-based inductors is described in detail. The measured performance of the PA IC is fully shown in this paper. The PA IC exhibits a saturated output power of 20.5 dBm and a peak power-added-efficiency (PAE) as high as 39.4% at a supply voltage of 4.0 V. Moreover, the PA IC has exhibited an excellent ITRS FoM of 82.0 dB.

KW - Adaptive bias

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KW - CMOS SOI

KW - High back-off efficiency

KW - Stacked-FET

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