A 28-GHz band highly linear power amplifier with novel adaptive bias circuit for cascode MOSFET in 56-nm SOI CMOS

Hiroya Sato; Masao Yanagisawa; Toshihiko Yoshimasu

doi:10.1109/EDSSC.2017.8126403

A 28-GHz band highly linear power amplifier with novel adaptive bias circuit for cascode MOSFET in 56-nm SOI CMOS

Hiroya Sato^*, Masao Yanagisawa, Toshihiko Yoshimasu

^*この研究の対応する著者

大学院情報生産システム研究科

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

This paper presents a highly linear 28-GHz band SOI CMOS power amplifier with an adaptive bias circuit for cascode MOSFET for next generation wireless communication. The power amplifier consists of a cascode MOSFET, the adaptive bias circuit and the input and output matching circuits. The power amplifier has exhibited a simulated output P1dB (1-dB gain compression point) of 19.2 dBm and a PAE of 39.0 %.

本文言語	English
ホスト出版物のタイトル	EDSSC 2017 - 13th IEEE International Conference on Electron Devices and Solid-State Circuits
出版社	Institute of Electrical and Electronics Engineers Inc.
ページ	1-2
ページ数	2
巻	2017-January
ISBN（電子版）	9781538629079
DOI	https://doi.org/10.1109/EDSSC.2017.8126403
出版ステータス	Published - 2017 12月 1
イベント	13th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2017 - Hsinchu, Taiwan, Province of China 継続期間: 2017 10月 18 → 2017 10月 20

Other

Other	13th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2017
国/地域	Taiwan, Province of China
City	Hsinchu
Period	17/10/18 → 17/10/20

ASJC Scopus subject areas

電子材料、光学材料、および磁性材料
ハードウェアとアーキテクチャ
電子工学および電気工学

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10.1109/EDSSC.2017.8126403

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引用スタイル

Sato, H., Yanagisawa, M., & Yoshimasu, T. (2017). A 28-GHz band highly linear power amplifier with novel adaptive bias circuit for cascode MOSFET in 56-nm SOI CMOS. In EDSSC 2017 - 13th IEEE International Conference on Electron Devices and Solid-State Circuits (Vol. 2017-January, pp. 1-2). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDSSC.2017.8126403

A 28-GHz band highly linear power amplifier with novel adaptive bias circuit for cascode MOSFET in 56-nm SOI CMOS. / Sato, Hiroya; Yanagisawa, Masao ; Yoshimasu, Toshihiko.
EDSSC 2017 - 13th IEEE International Conference on Electron Devices and Solid-State Circuits. Vol. 2017-January Institute of Electrical and Electronics Engineers Inc., 2017. p. 1-2.

研究成果: Conference contribution

Sato, H, Yanagisawa, M & Yoshimasu, T 2017, A 28-GHz band highly linear power amplifier with novel adaptive bias circuit for cascode MOSFET in 56-nm SOI CMOS. in EDSSC 2017 - 13th IEEE International Conference on Electron Devices and Solid-State Circuits. vol. 2017-January, Institute of Electrical and Electronics Engineers Inc., pp. 1-2, 13th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2017, Hsinchu, Taiwan, Province of China, 17/10/18. https://doi.org/10.1109/EDSSC.2017.8126403

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abstract = "This paper presents a highly linear 28-GHz band SOI CMOS power amplifier with an adaptive bias circuit for cascode MOSFET for next generation wireless communication. The power amplifier consists of a cascode MOSFET, the adaptive bias circuit and the input and output matching circuits. The power amplifier has exhibited a simulated output P1dB (1-dB gain compression point) of 19.2 dBm and a PAE of 39.0 %.",

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A 28-GHz band highly linear power amplifier with novel adaptive bias circuit for cascode MOSFET in 56-nm SOI CMOS

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