A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications

Fukashi Morishita; Isamu Hayashi; Hideto Matsuoka; Kazuhiro Takahashi; Kuniyasu Shigeta; Takayuki Gyohten; Mitsutaka Niiro; Hideyuki Noda; Mako Okamoto; Atsushi Hachisuka; Atsushi Amo; Hiroki Shinkawata; Tatsuo Kasaoka; Katsumi Dosaka; Kazutami Arimoto; Kazuyasu Fujishima; Kenji Anami; Tsutomu Yoshihara

doi:10.1109/JSSC.2004.837986

A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications

Fukashi Morishita^*, Isamu Hayashi, Hideto Matsuoka, Kazuhiro Takahashi, Kuniyasu Shigeta, Takayuki Gyohten, Mitsutaka Niiro, Hideyuki Noda, Mako Okamoto, Atsushi Hachisuka, Atsushi Amo, Hiroki Shinkawata, Tatsuo Kasaoka, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara

^*この研究の対応する著者

研究成果: Article › 査読

14 被引用数 (Scopus)

抄録

An embedded DRAM macro with a self-adjustable timing control (STC) scheme, a negative edge transmission scheme (NET), and a power-down data retention (PDDR) mode is developed. A 13.98-mm² 16-Mb embedded DRAM macro is fabricated in 0.13 μm logic-based embedded DRAM process. Co-salicide word lines and MIM capacitors are used for high-speed array operation. The delay timing variation of 36% for an RC delay can be reduced to 3.8% by using the STC scheme. The NET scheme transfers array control signals to local array blocks with high accuracy. Thereby, the test chip achieves 1.2-V 312-MHz random cycle operation even in the low-power process. 73-μW data retention power is realized by using the PDDR mode, which is 5% of conventional schemes.

本文言語	English
ページ（範囲）	204-210
ページ数	7
ジャーナル	IEEE Journal of Solid-State Circuits
巻	40
号	1
DOI	https://doi.org/10.1109/JSSC.2004.837986
出版ステータス	Published - 2005 1月

ASJC Scopus subject areas

電子工学および電気工学

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10.1109/JSSC.2004.837986

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Morishita, F., Hayashi, I., Matsuoka, H., Takahashi, K., Shigeta, K., Gyohten, T., Niiro, M., Noda, H., Okamoto, M., Hachisuka, A., Amo, A., Shinkawata, H., Kasaoka, T., Dosaka, K., Arimoto, K., Fujishima, K., Anami, K., & Yoshihara, T. (2005). A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications. IEEE Journal of Solid-State Circuits, 40(1), 204-210. https://doi.org/10.1109/JSSC.2004.837986

Morishita, F, Hayashi, I, Matsuoka, H, Takahashi, K, Shigeta, K, Gyohten, T, Niiro, M, Noda, H, Okamoto, M, Hachisuka, A, Amo, A, Shinkawata, H, Kasaoka, T, Dosaka, K, Arimoto, K, Fujishima, K, Anami, K & Yoshihara, T 2005, 'A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications', IEEE Journal of Solid-State Circuits, vol. 40, no. 1, pp. 204-210. https://doi.org/10.1109/JSSC.2004.837986

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abstract = "An embedded DRAM macro with a self-adjustable timing control (STC) scheme, a negative edge transmission scheme (NET), and a power-down data retention (PDDR) mode is developed. A 13.98-mm2 16-Mb embedded DRAM macro is fabricated in 0.13 μm logic-based embedded DRAM process. Co-salicide word lines and MIM capacitors are used for high-speed array operation. The delay timing variation of 36% for an RC delay can be reduced to 3.8% by using the STC scheme. The NET scheme transfers array control signals to local array blocks with high accuracy. Thereby, the test chip achieves 1.2-V 312-MHz random cycle operation even in the low-power process. 73-μW data retention power is realized by using the PDDR mode, which is 5% of conventional schemes.",

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AU - Morishita, Fukashi

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AU - Takahashi, Kazuhiro

AU - Shigeta, Kuniyasu

AU - Gyohten, Takayuki

AU - Niiro, Mitsutaka

AU - Noda, Hideyuki

AU - Okamoto, Mako

AU - Hachisuka, Atsushi

AU - Amo, Atsushi

AU - Shinkawata, Hiroki

AU - Kasaoka, Tatsuo

AU - Dosaka, Katsumi

AU - Arimoto, Kazutami

AU - Fujishima, Kazuyasu

AU - Anami, Kenji

AU - Yoshihara, Tsutomu

PY - 2005/1

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N2 - An embedded DRAM macro with a self-adjustable timing control (STC) scheme, a negative edge transmission scheme (NET), and a power-down data retention (PDDR) mode is developed. A 13.98-mm2 16-Mb embedded DRAM macro is fabricated in 0.13 μm logic-based embedded DRAM process. Co-salicide word lines and MIM capacitors are used for high-speed array operation. The delay timing variation of 36% for an RC delay can be reduced to 3.8% by using the STC scheme. The NET scheme transfers array control signals to local array blocks with high accuracy. Thereby, the test chip achieves 1.2-V 312-MHz random cycle operation even in the low-power process. 73-μW data retention power is realized by using the PDDR mode, which is 5% of conventional schemes.

AB - An embedded DRAM macro with a self-adjustable timing control (STC) scheme, a negative edge transmission scheme (NET), and a power-down data retention (PDDR) mode is developed. A 13.98-mm2 16-Mb embedded DRAM macro is fabricated in 0.13 μm logic-based embedded DRAM process. Co-salicide word lines and MIM capacitors are used for high-speed array operation. The delay timing variation of 36% for an RC delay can be reduced to 3.8% by using the STC scheme. The NET scheme transfers array control signals to local array blocks with high accuracy. Thereby, the test chip achieves 1.2-V 312-MHz random cycle operation even in the low-power process. 73-μW data retention power is realized by using the PDDR mode, which is 5% of conventional schemes.

KW - CMOS memory integrated circuits

KW - Embedded DRAM

KW - Mobile applications

KW - System-on-chip

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A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications

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