TY - GEN
T1 - A 333MHz random cycle DRAM using the floating body cell
AU - Hatsuda, Kosuke
AU - Fujita, Katsuyuki
AU - Ohsawa, Takashi
PY - 2005
Y1 - 2005
N2 - A Monte Carlo simulation shows that a DRAM using the floating body cell (FBC) realizes a 333MHz high-speed random cycle with an introduction of a symmetrical sense amplifier circuit and optimization of its current mirror ratio. Since the FBC DRAM having a superior affinity with logic LSI process is also shown to have its macro size smaller than the conventional 1T-1C DRAM, the FBC is a promising candidate for next generation embedded DRAM cells.
AB - A Monte Carlo simulation shows that a DRAM using the floating body cell (FBC) realizes a 333MHz high-speed random cycle with an introduction of a symmetrical sense amplifier circuit and optimization of its current mirror ratio. Since the FBC DRAM having a superior affinity with logic LSI process is also shown to have its macro size smaller than the conventional 1T-1C DRAM, the FBC is a promising candidate for next generation embedded DRAM cells.
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U2 - 10.1109/CICC.2005.1568656
DO - 10.1109/CICC.2005.1568656
M3 - Conference contribution
AN - SCOPUS:33847101893
SN - 0780390237
SN - 9780780390232
T3 - Proceedings of the Custom Integrated Circuits Conference
SP - 259
EP - 262
BT - Proceedings of the IEEE 2005 Custom Integrated Circuits Conference
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - IEEE 2005 Custom Integrated Circuits Conference
Y2 - 18 September 2005 through 21 September 2005
ER -