A 373 F                         2                          2D Power-Gated EE SRAM Physically Unclonable Function with Dark-Bit Detection Technique

Kunyang Liu; Yue Min; Xuan Yang; Hanfeng Sun; Hirofumi Shinohara

doi:10.1109/ASSCC.2018.8579315

A 373 F ² 2D Power-Gated EE SRAM Physically Unclonable Function with Dark-Bit Detection Technique

Kunyang Liu, Yue Min, Xuan Yang, Hanfeng Sun, Hirofumi Shinohara

研究成果: Conference contribution

12 被引用数 (Scopus)

抄録

This paper presents an Enhancement-Enhancement (EE) SRAM physically unclonable function (PUF) with a dark-bit detection technique based on an integrated Vss-bias generator. The EE SRAM PUF cell improves native stability to 0.21% bit-error rate (BER). Bit cells that are potentially unstable due to environmental variations or aging are detected via the lightweight bias generator to ensure stability, and the effectiveness is verified with experimental results of dark-bit detection performed at room temperature. Measurement results of 10 chips in 130-nm CMOS show that after masking the detected dark bits, 1.3×10 ^-6 BER is achieved across 0.8-1.4 V/-40-120 °C VT corners. The nMOS-only bit cell is also highly compact (i.e., 373 F ² ). Moreover, a 2D power-gating scheme is implemented for low operation energy, low standby power, and high attack tolerance.

本文言語	English
ホスト出版物のタイトル	2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings
出版社	Institute of Electrical and Electronics Engineers Inc.
ページ	161-164
ページ数	4
ISBN（電子版）	9781538664124
DOI	https://doi.org/10.1109/ASSCC.2018.8579315
出版ステータス	Published - 2018 12月 14
イベント	2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Tainan, Taiwan, Province of China 継続期間: 2018 11月 5 → 2018 11月 7

出版物シリーズ

名前	2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings

Conference

Conference	2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018
国/地域	Taiwan, Province of China
City	Tainan
Period	18/11/5 → 18/11/7

ASJC Scopus subject areas

ハードウェアとアーキテクチャ
電子工学および電気工学

文献へのアクセス

10.1109/ASSCC.2018.8579315

他のファイルとリンク

引用スタイル

Liu, K., Min, Y., Yang, X., Sun, H., & Shinohara, H. (2018). A 373 F ² 2D Power-Gated EE SRAM Physically Unclonable Function with Dark-Bit Detection Technique In 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings (pp. 161-164). Article 8579315 (2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASSCC.2018.8579315

A 373 F ² 2D Power-Gated EE SRAM Physically Unclonable Function with Dark-Bit Detection Technique . / Liu, Kunyang; Min, Yue; Yang, Xuan その他.
2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. p. 161-164 8579315 (2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings).

研究成果: Conference contribution

Liu, K, Min, Y, Yang, X, Sun, H & Shinohara, H 2018, A 373 F ² 2D Power-Gated EE SRAM Physically Unclonable Function with Dark-Bit Detection Technique in 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings., 8579315, 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 161-164, 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018, Tainan, Taiwan, Province of China, 18/11/5. https://doi.org/10.1109/ASSCC.2018.8579315

Liu K, Min Y, Yang X, Sun H, Shinohara H. A 373 F ² 2D Power-Gated EE SRAM Physically Unclonable Function with Dark-Bit Detection Technique In 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2018. p. 161-164. 8579315. (2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings). doi: 10.1109/ASSCC.2018.8579315

Liu, Kunyang ; Min, Yue ; Yang, Xuan その他. / A 373 F ² 2D Power-Gated EE SRAM Physically Unclonable Function with Dark-Bit Detection Technique 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 161-164 (2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings).

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title = " A 373 F 2 2D Power-Gated EE SRAM Physically Unclonable Function with Dark-Bit Detection Technique ",

abstract = " This paper presents an Enhancement-Enhancement (EE) SRAM physically unclonable function (PUF) with a dark-bit detection technique based on an integrated Vss-bias generator. The EE SRAM PUF cell improves native stability to 0.21% bit-error rate (BER). Bit cells that are potentially unstable due to environmental variations or aging are detected via the lightweight bias generator to ensure stability, and the effectiveness is verified with experimental results of dark-bit detection performed at room temperature. Measurement results of 10 chips in 130-nm CMOS show that after masking the detected dark bits, 1.3×10 -6 BER is achieved across 0.8-1.4 V/-40-120 °C VT corners. The nMOS-only bit cell is also highly compact (i.e., 373 F 2 ). Moreover, a 2D power-gating scheme is implemented for low operation energy, low standby power, and high attack tolerance.",

keywords = "EE SRAM, IoT, dark-bit masking, hardware security, physically unclonable function (PUF)",

author = "Kunyang Liu and Yue Min and Xuan Yang and Hanfeng Sun and Hirofumi Shinohara",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 ; Conference date: 05-11-2018 Through 07-11-2018",

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AU - Liu, Kunyang

AU - Min, Yue

AU - Yang, Xuan

AU - Sun, Hanfeng

AU - Shinohara, Hirofumi

PY - 2018/12/14

Y1 - 2018/12/14

N2 - This paper presents an Enhancement-Enhancement (EE) SRAM physically unclonable function (PUF) with a dark-bit detection technique based on an integrated Vss-bias generator. The EE SRAM PUF cell improves native stability to 0.21% bit-error rate (BER). Bit cells that are potentially unstable due to environmental variations or aging are detected via the lightweight bias generator to ensure stability, and the effectiveness is verified with experimental results of dark-bit detection performed at room temperature. Measurement results of 10 chips in 130-nm CMOS show that after masking the detected dark bits, 1.3×10 -6 BER is achieved across 0.8-1.4 V/-40-120 °C VT corners. The nMOS-only bit cell is also highly compact (i.e., 373 F 2 ). Moreover, a 2D power-gating scheme is implemented for low operation energy, low standby power, and high attack tolerance.

AB - This paper presents an Enhancement-Enhancement (EE) SRAM physically unclonable function (PUF) with a dark-bit detection technique based on an integrated Vss-bias generator. The EE SRAM PUF cell improves native stability to 0.21% bit-error rate (BER). Bit cells that are potentially unstable due to environmental variations or aging are detected via the lightweight bias generator to ensure stability, and the effectiveness is verified with experimental results of dark-bit detection performed at room temperature. Measurement results of 10 chips in 130-nm CMOS show that after masking the detected dark bits, 1.3×10 -6 BER is achieved across 0.8-1.4 V/-40-120 °C VT corners. The nMOS-only bit cell is also highly compact (i.e., 373 F 2 ). Moreover, a 2D power-gating scheme is implemented for low operation energy, low standby power, and high attack tolerance.

KW - EE SRAM

KW - IoT

KW - dark-bit masking

KW - hardware security

KW - physically unclonable function (PUF)

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A 373 F 2 2D Power-Gated EE SRAM Physically Unclonable Function with Dark-Bit Detection Technique

抄録